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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26556 is a quad, software-selectable T1, E1, or J1 transceiver with a cell/packet/TDM interface. It is composed of four framer/formatters + LIUs, and a UTOPIA (cell), POS-PHYTM (packet), and TDM backplane interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26556 also includes full-featured BERT devices per port, and an internal clock adapter useful for creating synchronous, high-frequency backplane timing. The DS26556 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation.
FEATURES

Four Independent, Full-Featured T1/E1/J1 Transceivers UTOPIA 2 and 3 Cell Interface POS-PHY 2 and 3 Packet Interface TDM Backplane Supports TDM Bus Rates from 1.544MHz to 16.384MHz Alarm Detection and Insertion Full-Featured BERT for Each Port AMI, B8ZS, HDB3, NRZ Line Coding Transmit Synchronizer BOC Message Controller (T1) One HDLC Controller per Framer Performance Monitor Counters RAI-CI and AIS-CI Support Internal Clock Generator (CLAD) Supplies 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz JTAG Test Port Single 3.3V Supply with 5V Tolerant Inputs 17mm x 17mm, 256-Pin BGA (1.00mm Pitch)
APPLICATIONS
Routers Add-Drop Multiplexers DSLAMs PBXs Switches Central Office Equipment
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
IMA ATM WAN Interface Customer-Premise Equipment

ORDERING INFORMATION
PART DS26556 DS26556N TEMP RANGE 0C to +70C -40C to +85C PINPACKAGE 256 BGA 256 BGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 012105
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
TABLE OF CONTENTS
1 2 BLOCK DIAGRAMS 9 FEATURES 10 2.1 FRAMER/LIU ................................................................................................................................................10
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Framer/Formatter................................................................................................................................................10 Line Interface (LIU) .............................................................................................................................................10 Clock Synthesizer ...............................................................................................................................................11 HDLC Controllers................................................................................................................................................11 Test and Diagnostics ..........................................................................................................................................11 General ...............................................................................................................................................................11 ATM ....................................................................................................................................................................12 HDLC ..................................................................................................................................................................12
2.2
CELL/PACKET INTERFACE .............................................................................................................................11
2.2.1 2.2.2 2.2.3
3 4 5
2.3 CONTROL PORT ...........................................................................................................................................12 BACKPLANE CONFIGURATION SCENERIOS 14 ACRONYMS AND GLOSSARY 18
PIN DESCRIPTIONS 19 5.1 SHORT PIN LIST ...........................................................................................................................................19 5.2 DETAILED PIN LIST .......................................................................................................................................22 6 DEVICE CONFIGURATION 30 7 FUNCTIONAL PIN TIMING 31 7.1 RECEIVER FUNCTIONAL TIMING DIAGRAMS....................................................................................................31 7.2 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ..............................................................................................32 7.3 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE FUNCTIONAL TIMING ............................................................34
7.3.1 7.3.2 7.3.3 7.3.4 UTOPIA Level 2 Functional Timing.....................................................................................................................34 UTOPIA Level 3 Functional Timing.....................................................................................................................38 POS-PHY Level 2 Functional Timing..................................................................................................................41 POS-PHY Level 3 Functional Timing..................................................................................................................45
8
FUNCTIONAL DESCRIPTION 47 8.1 CELL / PACKET INTERFACE DESCRIPTION......................................................................................................47
8.1.1 8.1.2 Reset Descriptions..............................................................................................................................................47 BIT / BYTE Ordering ...........................................................................................................................................47 General Description ............................................................................................................................................47 Features..............................................................................................................................................................48 System Interface Bus Controller .........................................................................................................................48 General Description ............................................................................................................................................52 Features..............................................................................................................................................................52 Transmit Cell/Packet Processor .........................................................................................................................53 Receive Cell/Packet Processor ..........................................................................................................................53 Cell Processor ....................................................................................................................................................54 Packet Processor................................................................................................................................................59 FIFO....................................................................................................................................................................61 System Loopback ...............................................................................................................................................62 T1 Loopbacks .....................................................................................................................................................63 H.100 (CT Bus) Compatibility .............................................................................................................................64 T1 Receive Status and Information ....................................................................................................................65 Receive AIS-CI and RAI-CI Detection ................................................................................................................67 T1 Receive-Side Digital Milliwatt Code Generation ............................................................................................67 T1 Error Count Registers ....................................................................................................................................67 T1 Receive Signaling Operation .........................................................................................................................68 Software Signaling..............................................................................................................................................68 Hardware Signaling ............................................................................................................................................68 Signaling Re-insertion.........................................................................................................................................68 Receive Signaling Freeze ...................................................................................................................................69 Fractional T1 Support (Gapped-Clock Mode) .....................................................................................................69 T1 Bit-Oriented Code (BOC) Controller ..............................................................................................................69
8.2
UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE............................................................................................47
8.2.1 8.2.2 8.2.6
8.3
ATM CELL / HDLC PACKET PROCESSING ....................................................................................................52
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8
8.4
T1 RECEIVE FRAMER DESCRIPTION AND OPERATION ....................................................................................63
8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 8.4.12 8.4.13
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8.4.14 8.4.15 8.4.16 8.4.17 8.4.18 Receive SLC-96 Operation .................................................................................................................................69 Receive FDL .......................................................................................................................................................69 Programmable In-Band Loop-Code Detection....................................................................................................70 Receive HDLC Controller....................................................................................................................................70 Receive HDLC Controller Example.....................................................................................................................71 T1 Per-Channel Loopback ..................................................................................................................................72 T1 Transmit DS0 Monitoring Function ................................................................................................................72 T1 Transmit Signaling Operation ........................................................................................................................72 T1 Transmit Per-Channel Idle Code Insertion ....................................................................................................73 T1 Transmit Channel Mark Registers .................................................................................................................73 Fractional T1 Support (Gapped Clock Mode) .....................................................................................................73 T1 Transmit Bit Oriented Code (BOC) Controller ...............................................................................................73 T1 Transmit FDL .................................................................................................................................................73 Transmit SLC-96 Operation ...............................................................................................................................74 Transmit HDLC Controller...................................................................................................................................74 HDLC Transmit Example ....................................................................................................................................74 Programmable In-Band Loop-Code Generator...................................................................................................75 Interfacing the T1 Tx Formatter to the BERT......................................................................................................76 T1 Transmit Synchronizer...................................................................................................................................76 H.100 (CT Bus) Compatibility .............................................................................................................................76 E1 Error Count Registers....................................................................................................................................77 DS0 Monitoring Function ....................................................................................................................................78 E1 Receive Signaling Operation.........................................................................................................................78 Fractional E1 Support (Gapped Clock Mode) .....................................................................................................79 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode) ................................................................................79 HDLC Overhead Control Receive Example........................................................................................................79 Interfacing the E1 Rx Framer to the BERT .........................................................................................................80 E1 Transmit Formatter Description and Operation .............................................................................................81 Automatic Alarm Generation...............................................................................................................................81 G.706 Intermediate CRC-4 Updating (E1 Mode Only)........................................................................................81 E1 Transmit DS0 Monitoring Function ................................................................................................................82 E1 Transmit Signaling Operation ........................................................................................................................82 Fractional E1 Support (Gapped Clock Mode) .....................................................................................................83 Additional (Sa) and International (Si) Bit Operation (E1 Mode) ..........................................................................83 E1 Transmit HDLC Controller .............................................................................................................................83 E1 HDLC Transmit Example...............................................................................................................................84 Interfacing the E1 Transmitter to the BERT ........................................................................................................85 E1 Transmit Synchronizer...................................................................................................................................85
8.5
T1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION.............................................................................72
8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 8.5.10 8.5.11 8.5.12 8.5.13 8.5.14
8.6
E1 RECEIVE FRAMER DESCRIPTION AND OPERATION ....................................................................................76
8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 8.6.9 8.6.10 8.6.11 8.6.12 8.6.13 8.6.14 8.6.15 8.6.16 8.6.17 8.6.18 8.6.19
9
LINE INTERFACE UNIT (LIU) 86 9.1 LIU TRANSMITTER........................................................................................................................................86 9.1.1 Pulse Shapes ...................................................................................................................................................86 9.1.2 Transmit Termination.......................................................................................................................................86 9.1.3 Power-Down and High-Z.................................................................................................................................86 9.1.4 Transmit All Ones ............................................................................................................................................86 9.1.5 Driver Fail Monitor............................................................................................................................................86 9.2 RECEIVER ....................................................................................................................................................89 9.2.1 Receiver Monitor Mode ...................................................................................................................................89 9.2.2 Peak Detector and Slicer ................................................................................................................................90 9.2.3 Clock and Data Recovery ...............................................................................................................................90 9.2.4 Receive Level Indicator...................................................................................................................................90 9.2.5 Loss of Signal ...................................................................................................................................................90 9.3 JITTER ATTENUATOR ....................................................................................................................................93 9.4 LIU LOOPBACKS ..........................................................................................................................................93
9.4.1 9.4.2 9.4.3 Analog Loopback ................................................................................................................................................93 Local Loopback...................................................................................................................................................94 Remote Loopback...............................................................................................................................................94
10 11
OVERALL REGISTER MAP
95
REGISTER MAPS AND DESCRIPTIONS 97 11.1 GLOBAL REGISTERS .....................................................................................................................................97
11.1.1 Global Control Registers.....................................................................................................................................97
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.1.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.3.1 11.3.2 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.4.9 11.4.10 11.4.11 11.4.12 11.4.13 11.4.14 11.4.15 11.4.16 11.4.17 Global Status Registers ....................................................................................................................................104 General Cell / Packet Registers........................................................................................................................111 Cell/Packet Status Registers ............................................................................................................................113 Transmit FIFO Registers...................................................................................................................................115 Transmit Cell Processor Registers ...................................................................................................................120 Transmit Packet Processor Registers ..............................................................................................................127 Receive Cell Processor Registers ....................................................................................................................133 Receive Packet Processor Registers ...............................................................................................................148 Receive FIFO Registers ...................................................................................................................................160 Transmit System Interface Registers................................................................................................................163 Receive System Interface Registers.................................................................................................................165 Receive Master-Mode Register ........................................................................................................................171 Interrupt Information Register ...........................................................................................................................172 T1 Receive Control Registers ...........................................................................................................................173 T1 Line-Code Violation Count Register (LCVCR).............................................................................................189 T1 Path-Code Violation Count Register (PCVCR)............................................................................................190 T1 Frames Out-of-Sync Count Register (FOSCR)............................................................................................191 DS0 Monitoring Function ..................................................................................................................................192 Receive Signaling Registers.............................................................................................................................193 T1 Receive Per-Channel Idle Code Insertion ...................................................................................................196 T1 Receive Channel Mark Registers ................................................................................................................197 Receive Fractional T1 Support (Gapped-Clock Mode) .....................................................................................198 Receive T1 Bit-Oriented Code (BOC) Controller ..............................................................................................199 Receive SLC-96 Operation ...............................................................................................................................200 Receive FDL .....................................................................................................................................................201 Programmable In-Band Loop-Code Detection..................................................................................................202 Receive HDLC Controller..................................................................................................................................208 Receive BERT ..................................................................................................................................................214
11.2 CELL / PACKET REGISTER DESCRIPTIONS ...................................................................................................110
11.3 SYSTEM INTERFACE REGISTERS .................................................................................................................163 11.4 RECEIVE T1 FRAMER REGISTERS ...............................................................................................................168
11.5 T1 TRANSMIT FRAMER................................................................................................................................216
11.5.1 Transmit-Master Mode Register .......................................................................................................................219 11.5.2 Interrupt Information Registers .........................................................................................................................219 11.5.3 T1 Transmit Control Registers ..........................................................................................................................220 11.5.4 T1 Transmit Status and Information..................................................................................................................225 11.5.5 T1 Per-Channel Loopback ................................................................................................................................228 11.5.6 T1 Transmit DS0 Monitoring Function ..............................................................................................................229 11.5.7 T1 Transmit Signaling Operation ......................................................................................................................229 11.5.8 T1 Transmit Per-Channel Idle Code Insertion ..................................................................................................233 11.5.9 T1 Transmit Channel Mark Registers ...............................................................................................................234 11.5.10 Fractional T1 Support (Gapped Clock Mode) ...................................................................................................235 11.5.11 T1 Transmit Bit Oriented Code (BOC) Controller .............................................................................................236 11.5.12 T1 Transmit FDL ...............................................................................................................................................237 11.5.13 Transmit SLC-96 Operation .............................................................................................................................237 11.5.14 Transmit HDLC Controller.................................................................................................................................238 Transmit Interrupt Mask Register 2.................................................................................................................................243 11.5.15 Programmable In-Band Loop-Code Generator.................................................................................................244 11.5.16 Interfacing the T1 Tx Formatter to the BERT....................................................................................................246 11.5.17 T1 Transmit Synchronizer.................................................................................................................................248
11.6 E1 RECEIVE FRAMER .................................................................................................................................250
11.6.1 11.6.2 11.6.3 11.6.4 11.6.5 11.6.6 11.6.7 11.6.8 11.6.9 11.6.10 11.6.11 11.6.12 11.6.13 11.6.14 E1 Receive Framer Description and Operation ................................................................................................253 Receive Master Mode Register.........................................................................................................................253 Interrupt Information Registers .........................................................................................................................254 E1 Receive Control Registers...........................................................................................................................254 E1 Receive Status and Information ..................................................................................................................257 E1 Error Count Registers..................................................................................................................................269 DS0 Monitoring Function ..................................................................................................................................272 E1 Receive Signaling Operation.......................................................................................................................273 E1 Receive Per-Channel Idle Code Insertion ...................................................................................................275 E1 Receive Channel Mark Registers ................................................................................................................276 Fractional E1 Support (Gapped Clock Mode) ...................................................................................................276 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode) ..............................................................................278 Receive Framer HDLC Controller .....................................................................................................................284 Interfacing the E1 Rx Framer to the BERT .......................................................................................................291
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver 11.7 E1 TRANSMIT FRAMER................................................................................................................................293
11.7.1 11.7.2 11.7.3 11.7.4 11.7.5 11.7.6 11.7.7 11.7.8 11.7.9 11.7.10 11.7.11 11.7.12 11.7.13 11.7.14 Transmit Master Mode Register........................................................................................................................296 Interrupt Information Registers .........................................................................................................................297 E1 Transmit Control Registers..........................................................................................................................297 E1 Transmit Status and Information .................................................................................................................300 Per-Channel Loopback .....................................................................................................................................302 E1 Transmit DS0 Monitoring Function ..............................................................................................................303 E1 Transmit Signaling Operation ......................................................................................................................304 E1 Transmit Per-Channel Idle Code Insertion ..................................................................................................308 E1 Transmit Channel Mark Registers ...............................................................................................................309 Fractional E1 Support (Gapped Clock Mode) ...................................................................................................309 Additional (Sa) and International (Si) Bit Operation (E1 Mode) ........................................................................310 E1 Transmit HDLC Controller ...........................................................................................................................317 Interfacing the E1 Transmitter to the BERT ......................................................................................................323 E1 Transmit Synchronizer.................................................................................................................................325
LINE INTERFACE UNIT (LIU) 327 12.1 LIU REGISTERS .........................................................................................................................................328 13 BIT ERROR RATE TESTER (BERT) 335 13.1 BERT REGISTER BIT DESCRIPTIONS ..........................................................................................................336 14 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 342 14.1 TAP CONTROLLER STATE MACHINE ...........................................................................................................343 14.2 INSTRUCTION REGISTER .............................................................................................................................345 14.3 TEST REGISTERS .......................................................................................................................................346 15 PIN ASSIGNMENT 347 16 17 18 19 PACKAGE MECHANICAL INFORMATION PACKAGE THERMAL INFORMATION ABSOLUTE MAXIMUM RATINGS 348 349 350
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AC TIMING 351 19.1 TRANSMIT TDM PORT AC CHARACTERISTICS .............................................................................................353 19.2 RECEIVE TDM PORT AC CHARACTERISTICS ...............................................................................................354 19.3 HIGH SPEED PORT AC CHARACTERISTICS ..................................................................................................355 19.4 SYSTEM INTERFACE AC CHARACTERISTICS.................................................................................................356 19.5 MICROPROCESSOR BUS AC CHARACTERISTICS ..........................................................................................358 19.6 JTAG INTERFACE TIMING ...........................................................................................................................361 20 REVISION CHANGE HISTORY 362
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 1-1 Block Diagram .............................................................................................................................................9 Figure 2-1 Backplane Interface Diagram For Port 1 of 4 ............................................................................................13 Figure 3-1 ATM Over 4 Ports......................................................................................................................................14 Figure 3-2 IP Over 4 T1/E1 Ports ...............................................................................................................................14 Figure 3-3 IP Over 2 Ports, TDM Over 2 Ports ...........................................................................................................14 Figure 3-4 ATM Over 2 Ports, 2 Ports Combined Into High Speed TDM ...................................................................14 Figure 3-5 Fractional ATM Over 4 Ports With Fractional TDM Access to Each Port .................................................15 Figure 3-6 8 Port High Speed TDM Bus .....................................................................................................................15 Figure 7-1 Receive TDM Signals ................................................................................................................................31 Figure 7-2 Receive TDM Signals, Details ...................................................................................................................31 Figure 7-3 Transmit TDM Signals...............................................................................................................................32 Figure 7-4 Transmit TDM Signals, Details..................................................................................................................32 Figure 7-5 Two Port High Speed TDM Bus ................................................................................................................33 Figure 7-6 Four Port High Speed TDM Bus................................................................................................................34 Figure 7-7 UTOPIA Level 2 Transmit Cell Transfer Direct Mode ...............................................................................35 Figure 7-8 UTOPIA Level 2 Receive Cell Transfer Direct Mode ................................................................................35 Figure 7-9 UTOPIA Level 2 Transmit Multiple Cell Transfer Polled Mode .................................................................36 Figure 7-10 UTOPIA Level 2 Receive Multiple Cell Transfer Polled Mode.................................................................37 Figure 7-11 UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer .................................................................37 Figure 7-12 UTOPIA Level 3 Transmit Multiple Cell Transfer Direct Mode ................................................................38 Figure 7-13 UTOPIA Level 3 Transmit Multiple Cell Transfer Polled Mode ...............................................................39 Figure 7-14 UTOPIA Level 3 Receive Multiple Cell Transfer Direct Mode .................................................................40 Figure 7-15 UTOPIA Level 3 Receive Multiple Cell Transfer Polled Mode.................................................................40 Figure 7-16 Transmit Multiple Packet Transfer to Different PHY ports (direct status mode) .....................................41 Figure 7-17 POS-PHY Level 2 Receive Multiple Packet Transfer from Different PHY Ports/Devices (direct status mode) .................................................................................................................................................................42 Figure 7-18 POS-PHY Level 2 Transmit Multiple Packet Transfer to Different PHY Ports (polled status mode).......43 Figure 7-19 POS-PHY Level 2 Receive Multiple Packet Transfer (polled status mode) ............................................44 Figure 7-20 POS-PHY Level 3 Transmit Multiple Packet Transfer In-Band Addressing ............................................45 Figure 7-21 POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing .............................................46 Figure 8-1 Normal Packet Format in 16-Bit Mode ......................................................................................................48 Figure 8-2 Byte Reordered Packet Format in 16-Bit Mode.........................................................................................49 Figure 8-4 Receive DSS Scrambler Synchronization State Diagram .........................................................................56 Figure 8-5 Cell Delineation State Diagram .................................................................................................................57 Figure 8-6 HEC Error Monitoring State Diagram ........................................................................................................58 Figure 8-7 Cell Format for 53-Byte Cell With 16-Bit Data Bus....................................................................................58 Figure 8-8 Cell Format for 52-Byte Cell With 16-Bit Data Bus....................................................................................59 Figure 8-9 Remote Loopback .....................................................................................................................................63 Figure 8-10 Payload Loopback ...................................................................................................................................63 Figure 8-11 Framer Loopback ....................................................................................................................................64 Figure 8-12 HSSYNC Input in H.100 (CT Bus) Mode................................................................................................65 Figure 8-13 Receive HDLC Example..........................................................................................................................71 Figure 8-14 HDLC Message Transmit Example .........................................................................................................75 Figure 8-15 HSSYNC Input in H.100 (CT Bus) Mode.................................................................................................77 Figure 8-16 Receive HDLC Example..........................................................................................................................80 Figure 8-17 CRC Update Flow Diagram .....................................................................................................................82 Figure 8-18 Time Slot Numbering Schemes...............................................................................................................83 Figure 8-19 E1 HDLC Message Transmit Example....................................................................................................84 Figure 9-1 T1/J1 Transmit Pulse Templates ..............................................................................................................87 Figure 9-2 E1 Transmit Pulse Templates ...................................................................................................................88 Figure 9-3 Typical Monitor Operation .........................................................................................................................89 Figure 9-4 Jitter Tolerance..........................................................................................................................................92 Figure 9-5 Jitter Attenuation........................................................................................................................................93 Figure 11-1 Transmit FIFO Register Map.................................................................................................................115 Figure 11-2 E1 Sync/Resync Criteria......................................................................................................................255 Figure 14-1 JTAG Functional Block Diagram ...........................................................................................................342 Figure 14-2 Tap Controller State Diagram................................................................................................................343 Figure 15-1 DS26556 Pin Assignments--256 lead BGA.........................................................................................347 6 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Figure 19-1 Clock Period and Duty Cycle Definitions ...............................................................................................351 Figure 19-2 Rise Time, Fall Time, and Jitter Definitions...........................................................................................351 Figure 19-3 Hold, Setup, and Delay Definitions (Rising Clock Edge) .......................................................................351 Figure 19-4 Hold, Setup, and Delay Definitions (Falling Clock Edge) ......................................................................352 Figure 19-5 To/From High-Z Delay Definitions (Rising Clock Edge) ........................................................................352 Figure 19-6 To/From High-Z Delay Definitions (Falling Clock Edge)........................................................................352 Figure 19-7 Intel Bus Read Timing (BTS = 0)...........................................................................................................359 Figure 19-8 Intel Bus Write Timing (BTS = 0)...........................................................................................................359 Figure 19-9 Motorola Bus Read Timing (BTS = 1) ...................................................................................................360 Figure 19-10 Motorola Bus Write Timing (BTS = 1) .................................................................................................360 Figure 19-11 JTAG Interface Timing Diagram..........................................................................................................361
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
LIST OF TABLES
Table 3-1 Framer LIU Compliance .............................................................................................................................16 Table 3-2 Cell/Packet Interface Compliance ..............................................................................................................17 Table 5-1 Short Pin List ..............................................................................................................................................19 Table 5-2 Pin Descriptions..........................................................................................................................................22 Table 8-1 T1 Alarm Criteria ........................................................................................................................................66 Table 8-2 E1 Line Code Violation Counting Options ..................................................................................................78 Table 9-1 Loss Criteria T1.231, G.775 and ETSI 300 233 Specifications ..................................................................91 Table 10-1 Overall Register Map ................................................................................................................................95 Table 10-2 Per Port Register Map ..............................................................................................................................96 Table 11-1 Global Register Map .................................................................................................................................97 Table 11-2 General Cell / Packet Register Map .......................................................................................................111 Table 11-3 Transmit Cell Processor Register Map...................................................................................................120 Table 11-4 Transmit Packet Processor Register Map..............................................................................................127 Table 11-5 Receive Cell Processor Register Map ....................................................................................................133 Table 11-6 Receive Packet Processor Register Map ...............................................................................................148 Table 11-7 Receive FIFO Register Map ...................................................................................................................160 Table 11-8 Transmit System Interface Register Map ...............................................................................................163 Table 11-9 Receive System Interface Register Map ................................................................................................165 Table 11-10 T1 Receive Framer Register Map ........................................................................................................168 Table 11-11 T1 Line-Code Violation Counting Options ............................................................................................189 Table 11-12 T1 Path-Code Violation Counting Arrangements .................................................................................190 Table 11-13 T1 Frame Out-of-Sync Counting Arrangements...................................................................................191 Table 11-14 T1 Transmit Framer Register Map .......................................................................................................216 Table 11-15 E1 Receive Framer Register Map ........................................................................................................250 Table 11-16 E1 Alarm Criteria ..................................................................................................................................258 Table 11-17 E1 Line Code Violation Counting Options ............................................................................................270 Table 11-18 E1 Transmit Framer Register Map .......................................................................................................293 Table 11-19 E1 Transmit Signaling - CAS Format ...................................................................................................304 Table 11-20 E1 Transmit Signaling - CCS Format ..................................................................................................304 Table 12-1 LIU Register Map....................................................................................................................................327 Table 12-2 Internal Transmit Termination Select......................................................................................................329 Table 12-3 E1 Transmit Pulse Shape Selection .......................................................................................................330 Table 12-4 T1/J1 Transmit Pulse Shape Selection ..................................................................................................330 Table 12-5 Receive Level Indication.........................................................................................................................333 Table 12-6 Internal Receive Termination Selection ..................................................................................................334 Table 12-7 Monitor Gain and Maximum Receive Sensitivity Selection.....................................................................334 Table 13-1 BERT Register Map................................................................................................................................335 Table 14-1 Instruction Codes for IEEE 1149.1 Architecture .....................................................................................345 Table 14-2 ID Code Structure ...................................................................................................................................346 Table 17-1 Thermal Characteristics..........................................................................................................................349 Table 18-1 Absolute Maximum Ratings....................................................................................................................350 Table 18-2 Recommended DC Operating Conditions ..............................................................................................350 Table 18-3 Capacitance............................................................................................................................................350 Table 18-4 DC Operating Characteristics .................................................................................................................350 Table 19-1 Transmit TDM Port Timing .....................................................................................................................353 Table 19-2 Receive TDM Port Timing ......................................................................................................................354 Table 19-3 Receive TDM Port Timing ......................................................................................................................355 Table 19-4 System Interface Level 2 Timing ............................................................................................................356 Table 19-5 System Interface Level 3 Timing ............................................................................................................357 Table 19-6 AC Characteristics--Microprocessor Bus Timing ..................................................................................358 Table 19-7 JTAG Interface Timing............................................................................................................................361
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
1 BLOCK DIAGRAMS
Figure 1-1 Block Diagram
TXENABLE TCLKn TSYNCn TSERIn TSEROn HSYSCLK HSSYNC HTDATA HTSIG
DS26556
Transmit DS1/E1 LIU
Analog LB Local LB
Per Port TDM Interface DS1/ E1 TRANSMIT FORMATTER
High Speed Bus Interface Tx Cell Processor Tx Packet Processor
JITTER ATTENUATOR
TRINGn
Payload LB
Remote LB
Framer LB
HDLC
RX BERT Rx Packet Processor Rx Cell Processor
SLB
TX BERT
Utopia / POS-PHY Interface
TTIPn
Tx FIFO
TSCLK TADR[4:0] TDATA[15:0] TPRTY TEN TDXA[4:2] TDXA[1]/TPXA TSOX TSPA TEOP TSX TMOD TERR RSCLK RADR[4:0] RDATA[15:0] RPRTY REN RDXA[1]/RPXA /RSX RDXA[4:2] RSOX REOP RVAL RMOD RERR
RTIPn RRINGn
DS1/E1 Receive LIU
DS1/E1 RECEIVE FRAMER
Per Port TDM Interface
High Speed Bus Interface
Rx FIFO
Clock Rate Adapter
IEEE P1149.1 JTAG Test Access Port
MICROPROCESSOR INTERFACE
REFCLK
BPCLK
JTRST JTCLK JTMS JTDI JTDO
RSERn RCLKn RSYNCn RCHMRKn RM_RFSYNCn RCLKOn
RESET
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HIZ RLOSn RLOFn/LOTCn ROCDn RLCDn
MCLK
HSYSCLK HSSYNC HRDATA HRSIG
BTS ALE CS RD/DS WR/ R/W
A[12:0]
D[7:0]
INT
n = port #
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
2 FEATURES
2.1
2.1.1

Framer/LIU
Framer/Formatter
Fully Independent Transmit and Receive Functionality Full Receive and Transmit Path Transparency T1 Framing Formats D4 and ESF per T1.403, and Expanded SLC-96 Support (TR-TSY-008) E1 FAS Framing and CRC-4 Multiframe per G.704/G.706 and G.732 CAS Multiframe Detailed Alarm and Status Reporting with Optional Interrupt Support Large Path and Line Error Counters for T1: BPV, CV, CRC6, and Framing Bit Errors E1: BPV, CV, CRC4, E-Bit, and Frame Alignment Errors Timed or Manual Update Modes DS1 Idle Code Generation on a Per-Channel Basis in Both Transmit and Receive Paths User-Defined Digital Milliwatt ANSI T1.403-1998 Support G.965 V5.2 Link Detect Ability to Monitor One DS0 Channel in Both the Transmit and Receive Paths In-Band Repeating Pattern Generators and Detectors Three Independent Detectors Patterns from 1 to 8 bits or 16 bits in Length Bit Oriented Code (BOC) Support Signaling Support Software based Interrupt Generated on Change of Signaling Data Hardware Pins Provided to Indicate Loss of Frame, Loss of Signal and Loss-of-Transmit Clock (LOTC) Automatic RAI Generation to ETS 300 011 Specifications RAI-CI and AIS-CI Support Expanded Access to Sa and Si Bits Option to Extend Carrier Loss Criteria to a 1ms Period as per ETS 300 233 Japanese J1 Support Ability to Calculate and Check CRC6 According to the Japanese Standard Ability to Generate Yellow Alarm According to the Japanese Standard

2.1.2

Line Interface (LIU)
Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Fully software configurable Short-haul and long-haul applications Automatic receive sensitivity adjustments Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1 applications Receive level indication in 2.5dB steps from -42.5dB to -2.5dB Internal receive termination option for 75, 100, and 120W lines Internal transmit termination option for 75, 100, and 120W lines Monitor application gain settings of 20dB, 26dB, and 32dB G.703 receive synchronization-signal mode Flexible transmit waveform generation T1 DSX-1 line build-outs T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75W coax and 120W twisted cables AIS generation independent of loopbacks Alternating ones and zeros generation Square-wave output Open-drain output option NRZ format option 10 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Transmitter power-down Transmitter 50mA short-circuit limiter with current-limit-exceeded indication Transmit open-circuit-detected indication
2.1.3
Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz Derived from recovered receive clock
2.1.4
HDLC Controllers
HDLC Engine (One per Framer): Independent 64-byte Rx and Tx Buffers with Interrupt Support Access FDL, Sa, or Single DS0 Channel Compatible with Polled or Interrupt Driven Environments
2.1.5
Test and Diagnostics

Full-Featured BERTs n y * Programmable PRBS pattern - The Pseudo Random Bit Sequence (PRBS) polynomial (x + x + 1) and n seed are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2 - 1). * Programmable repetitive pattern - The repetitive pattern length and pattern are programmable (the length n n = 1 - 32 and pattern = 0 - 2 - 1). * 24-bit error count and 32-bit bit count registers * Programmable bit error insertion - Errors can be inserted individually, on a pin transition, or at a specific n rate. The rate 1/10 is programmable (n = 1 to 7). -3 * Pattern synchronization at a 10 BER - Pattern synchronization will be achieved even in the presence of a -3 random Bit Error Rate (BER) of 10 . BPV Insertion F-Bit Corruption for Line Testing Loopbacks Remote Local Per-Channel IEEE 1149.1 Support
2.2
2.2.1
*
Cell/Packet Interface
General
Programmable system interface type - When performing cell mapping/demapping, the system interface can be programmed as a UTOPIA Level 2 Bus or a UTOPIA Level 3 Bus or a POS-PHY Level 2 or Level 3 Bus. When performing packet mapping/demapping, the system interface can be programmed as a POS-PHY Level 2 Bus or a POS-PHY Level 3 Bus. Selectable system interface bus width - The data bus can be a 16-bit or 8-bit bus. Supports clock speeds up to 52 MHz. Supports multiple ports on the system interface - Each line has its own port address for access via the system interface. Programmable system interface port address - The address assigned to each system interface port is programmable to allow multiple devices to operate on the same bus. Supports per port system loopback - Each port has can be placed in system loopback which causes cells/packets from the transmit FIFO to looped back to the receive FIFO. System interface bit/byte reordering - In 16-bit mode the order of the bytes as transferred across the system interface is programmable, i.e., the first byte received/transmitted can be transferred in ([15:8]) or [7:0]. The order of the bits as transferred across the system interface is programmable on a per port basis, i.e., the first bit received/transmitted can be transferred in bit position 7 (15 and 7) or bit position 0 (8 and 0).
* * * * * *
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
2.2.2
*
ATM
* * * * *
* * * * *
Programmable HEC insertion and extraction - The transmit side can be programmed to accept cells from the system interface that do or do not contain a HEC byte. If cells are transferred without a HEC byte, the HEC byte will be computed and inserted. If cells are transferred with a HEC byte, then the transferred HEC byte can be programmed to be passed through or overwritten with a newly calculated HEC. The receive side can be programmed to send cells to the system interface that do or don't contain the HEC byte. Programmable errored cell insertion - An HEC error mask can be programmed for insertion of a single or multiple errors individually or continuously at a programmable rate. Programmable transmit cell synchronization - The transmit data line can be provisioned to be bit synchronous, byte synchronous, or cell synchronous. HEC based cell delineation - Cell delineation is determined from the HEC. Programmable header cell pass-through - Receive cell filtering can pass-through only those cells that matching a programmable header value. Selectable idle/unassigned/invalid/programmable header cell padding and filtering - Transmit cell padding can be programmed for idle cell or programmable header cell padding. The padded cell payload byte contents are also programmable. Receive cell filtering can be programmed for any combination of idle cell, unassigned cell, invalid cell, or programmable header cell filtering. Or, all cell filtering can be disabled. Optional header error correction - Receive side single bit header error correction can enabled. Separate corrected and uncorrected errored cell counts - Separate counts of errored cells containing a corrected HEC error, and cells containing non-corrected HEC errors are kept. Optional HEC uncorrected errored cell filtering - Uncorrected errored cell extraction can be disabled. Selectable cell scrambling/descrambling - Cell scrambling and/or descrambling can be disabled. The 43 scrambling can be a self-synchronous scrambler (x + 1) over the payload only, a self-synchronous scrambler 31 28 over the entire cell, or a Distributed Sample Scrambler (x + x + 1). Optional HEC calculation coset polynomial addition - The performance of coset polynomial addition during HEC calculation can be disabled.
2.2.3
*
HDLC
* * * * * * * * *
Programmable FCS insertion and extraction - The transmit side can be programmed to accept packets from the system interface that do or don't contain FCS bytes. If packets are transferred without FCS bytes, the FCS will be computed and appended to the packet. If packets are transferred with FCS bytes, then the FCS can be programmed to be passed through or overwritten with a newly calculated FCS. The receive side can be programmed to send packets to the system interface that do or don't contain FCS bytes. Programmable transmit packet synchronization - The transmit data line can be provisioned to be bit synchronous or byte synchronous. Programmable FCS type - The FCS can be programmed to be a 16-bit FCS or a 32-bit FCS. Supports FCS error insertion - FCS error insertion can be programmed for insertion of errors individually or continuously at a programmable rate. Supports bit or byte stuffing/destuffing - The bit or byte synchronous mode determines the bit or byte stuffing/destuffing. Programmable packet size limits - The receive side can be programmed to abort packets over a programmable maximum size or under a programmable minimum size. The maximum packet size allowed is 65,535 bytes. Selectable packet scrambling/descrambling - Packet scrambling and/or descrambling can be disabled. Separate FCS errored packet and aborted packet counts - Separate counts of aborted packets, size violation packets, and FCS errored packets are kept. Optional errored packet filtering - Errored packet extraction can be disabled Programmable inter-frame fill - The transmit inter-frame fill value is programmable.
2.3

Control Port
8-Bit Parallel Control Port Intel or Motorola Nonmultiplexed Support Flexible Status Registers Support Polled, Interrupt, or Hybrid Program Environments Software Reset Supported Hardware Reset Pin 12 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 2-1 Backplane Interface Diagram For Port 1 of 4
MULTIFRAME SYNC FRAME SYNC CHANNEL MARKER RECOVERED CLOCK RECOVERED DATA RSYNC RCHMRK RCLK RSER PORT 1 RECEIVE TDM BUS
CLOCK DATA RECEIVE FRAMER SYNCIN SYNCOUT
CHANNEL MARKER CLOCK SYNC DATA RECEIVE CELL / PACKET BUS (COMMON TO ALL PORTS)
ELASTIC STORE SIG BUFFER
PORTS 2-4
RECEIVE CELL / PACKET CONTROLLER CLOCK OUT SYNC OUT SYNC IN RDATA RSIG TDATA TSIG HSYSCLK HSSYNC HRDATA HRSIG HTDATA HTSIG HIGH SPEED MULTIPLEXED BUS
PORTS 2-4
HIGH SPEED MULTIPLEXED CONTROLLER
CHANNEL MARKER TRANSMIT CLOCK
TCHMRK TCLK TSYNC (I/O) TSERI TSERO CLOCK DATA DATA OUT SYNC IN CLOCK CHANNEL MARKER TRANSMIT CELL / PACKET BUS (COMMON TO ALL PORTS) PORT 1 TRANSMIT TDM BUS
TO TX LIU
TRANSMIT SYNC TRANSMIT DATA
TRANSMIT SYNC OUT TRANSMIT FRAMER
SYNCIN TX ELASTIC STORE SIG BUFFER
PORTS 2-4
TRANMSIT CELL / PACKET CONTROLLER
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
3 BACKPLANE CONFIGURATION SCENERIOS
Figure 3-1 ATM Over 4 Ports
T1/E1 #1 T1/E1 #2 T1/E1 #3 T1/E1 #4
XCEIVER XCEIVER XCEIVER XCEIVER
UTOPIA I/F
ATM
Figure 3-2 IP Over 4 T1/E1 Ports
T1/E1 #1 T1/E1 #2 T1/E1 #3 T1/E1 #4
XCEIVER XCEIVER XCEIVER XCEIVER
PACKET I/F
IP
Figure 3-3 IP Over 2 Ports, TDM Over 2 Ports
T1/E1 #1 T1/E1 #2 T1/E1 #3 T1/E1 #4
XCEIVER XCEIVER XCEIVER XCEIVER
PACKET I/F
IP TDM TDM
Figure 3-4 ATM Over 2 Ports, 2 Ports Combined Into High Speed TDM
T1/E1 #1 T1/E1 #2 T1/E1 #3 T1/E1 #4
XCEIVER XCEIVER XCEIVER XCEIVER
UTOPIA I/F ELASTIC BUFFERS
ATM 2X HIGH SPEED TDM
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 3-5 Fractional ATM Over 4 Ports With Fractional TDM Access to Each Port
T1/E1 #1 T1/E1 #2 T1/E1 #3 T1/E1 #4
XCEIVER XCEIVER XCEIVER XCEIVER
UTOPIA I/F
ATM
FRACTIONAL TDM ACCESS TO PORT 1 FRACTIONAL TDM ACCESS TO PORT 2 FRACTIONAL TDM ACCESS TO PORT3 FRACTIONAL TDM ACCESS TO PORT4
Figure 3-6 8 Port High Speed TDM Bus
DS26556 #1
T1/E1 PORT 1 T1/E1 PORT 2 T1/E1 PORT 3 T1/E1 PORT 4
HSYSCLK HSSYNC HRSIG HTSIG HRDATA HTDATA
16.384 MHz System Clock In System 8KHz Frame Sync In TDM Receive Signaling Out TDM Transmit Signaling In TDM Receive Data Out TDM Transmit Data In
DS26556 #2
T1/E1 PORT 5 T1/E1 PORT 6 T1/E1 PORT 7 T1/E1 PORT 8
HSYSCLK HSSYNC HRSIG HTSIG HRDATA HTDATA
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Standards Compliance
The DS26556 conforms to the applicable parts of the following standards.
Table 3-1 Framer LIU Compliance
SPECIFICATION ANSI T1.102-1993 T1.107-1995 T1.231-1997 T1.403-1999 AT&T TR54016 TR62411 ITU G.704, 1995 G.706, 1991 G.732, 1993 G.736, 1993 G.775, 1994 G.823, 1993 I.431, 1993 O.151, 1992 O.161, 1988 ETSI ETS 300 011, 1998 ETS 300 166, 1993 ETS 300 233, 1994 CTR 4, 1995 I.432, 1993 CTR 12, 1993 CTR 13, 1996 TTC JT-G.704, 1995 JTI.431, 1995 Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736 kbit/s Hierarchical Levels Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704 Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy Primary Rate User-Network Interface--Layer 1 Specification Error Performance Measuring Equipment Operating at the Primary Rate and Above In-service code violation monitors for digital systems Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part 1: Layer 1 specification Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using the 2048 kbit/s-based plesiochronous or synchronous digital hierarchies Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access B-ISDN User-Network Interface--Physical Layer Specification-ITU-T Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048 kbit/s digital unstructured leased lines (D2048U) attachment requirements for terminal equipment interface Business Telecommunications (BTC); 2048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface Frame Structures on Primary and Secondary Hierarchical Digital Interfaces ISDN Primary Rate User-Network Interface Layer 1 Specification TITLE Digital Hierarchy--Electrical Interfaces Digital Hierarchy--Formats Specification Digital Hierarchy--Layer 1 In-Service Digital Transmission Performance Monitoring Network and Customer Installation Interfaces--DS1 Electrical Interface Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Superframe Format High Capacity Digital Service Channel Interface Specification
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Table 3-2 Cell/Packet Interface Compliance
Organization IETF OIF ATM Forum Number RFC 1662 RFC 2615 OIF-SPI3-01.0 af-uni-0010.002 af-phy-0039.000 af-bici-0013.003 af-phy-0136.000 af-phy-0143.000 I.361 I.432.1 Title PPP in HDLC-like Framing PPP over SONET System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices ATM User-Network Interface Specification, Version 3.1 UTOPIA Level 2 Physical Layer Interface Specification BISDN Inter Carrier Interface (B-ICI) Specification Version 2.0 (Integrated) UTOPIA Level 3 Physical Layer Interface Specification Frame-based ATM Interface (Level 3) B-ISDN ATM Layer Specification B-ISDN User-Network Interface - Physical Layer Specification - General Characteristics
ITU-T
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
4 ACRONYMS AND GLOSSARY
Definition of the terms used in this data sheet: Acronyms * * * * * * * * * * ATM - Asynchronous Transfer Mode CC52 - Clear Channel 52 Mbps (STS-1 Clock Rate) CLAD - Clock Rate Adapter CLR - Clear Channel Mode DSS - Distributed Sample Scrambler FFRAC - Flexible Fractional Mode FRM - Frame Mode HDLC - High Level Data Link Control SPI-3 - same as POS-PHY L3 TDM - Time Division Multiplexing
Glossary * Cell - ATM cell * Clear Channel - A data stream with no framing included * Fractional - Uses only a portion of available payload for data, also known as subrate * Octet Aligned - Byte aligned * Packet - HDLC packet * Subrate - See Fractional
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
5 PIN DESCRIPTIONS
5.1 Short Pin List
Table 5-1 Short Pin List
Pin # Name Type Function Network Interface Signals Transmit Tip Transmit Ring Secondary Transmit Tip Secondary Transmit Ring Receive Tip Receive Ring Transmit High Impedance Enable Backplane TDM Signals Transmit Serial Data Out Transmit Serial Data In Transmit Clock Transmit Sync Transmit Channel Marker Receive Serial Data Receive Clock Out Receive Sync Receive Multiframe Sync / Frame Sync Receive Channel Marker Backplane High Speed TDM Signals High Speed Bus Transmit Data High Speed Bus Transmit Signaling Data High Speed Bus Receive Data High Speed Bus Receive Signaling Data High Speed Bus System Clock High Speed Bus System Sync Status Signals Receive Out of Cell Delineation Receive Loss of Cell Delineation Receive Loss of Frame / Loss of Transmit Clock Receive Loss of Signal Microcontroller Interface Address Bus[12:0] Port 4 T1 T3 T2 R3 P1 P2 Port 3 J1 J3 J2 K3 L1 L2 Port 2 H1 H3 H2 G3 F1 F2 M5 D6 F3 A6 E3 B6 B5 E6 A5 K4 C6 T9 P9 R9 L10 M9 N9 R11 L11 N4 L3 N14 N11 L6 M4 P14 P11 G4 H4 F7 E7 D7 C7 B7 A7 E8 C8 A8 B8 D8 F8 B9 M11 T11 F5 F4 Port 1 A1 A3 A2 B3 C1 C2
TTIP[4:1] TRING[4:1] STTIP{4:1] STRING[4:1] RTIP[4:1] RRING[4:1] TXENABLE TSERO[4:1] TSERI[4:1] TCLK[4:1] TSYNC[4:1] TCHMRK[4:1] RSER[4:1] RCLKO[4:1] RSYNC[4:1] RM_RFSYNC[4:1] RCHMRK[4:1] HTDATA HTSIG HRDATA HRSIG HSYSCLK HSSYNC ROCD[4:1] RLCD[4:1] RLOF/LOTC[4:1] RLOS[4:1] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
O O O O I I I O I I I/O O O O O O O I I O O I I/O O O O O I
M6 R4 P4 P5 N5 T5 L7 R5 L4 T4
P6 T6 N3 R6 P3 N7 M7 L8 L5 N6
D5 A4 C5 C3 F6 E5 C4 D3 J4 B4
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Pin # Name DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] CS WR(R/W) RD(DS) BTS INT HIZ
JTRST JTCLK JTMS JTDI JTDO RESET MCLK REFCLK BPCLK
Type I/O
Function Data Bus[7:0]
Port 4
Port 3
Port 2
Port 1
TSCLK TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] TDATA[15] TDATA[14] TDATA[13] TDATA[12] TDATA[11] TDATA[10] TDATA[9] TDATA[8] TDATA[7] TDATA[6] TDATA[5] TDATA[4] TDATA[3] TDATA[2] TDATA[1] TDATA[0] TPAR TEN TDXA[1] / TPXA
Chip Select Write Input (Read/Write) Read Input (Data Strobe) Bus Type Select Interrupt High Z JTAG I JTAG Reset I JTAG Clock Ipu JTAG Mode Select Ipu JTAG Data Input O JTAG Data Output Clock Signals I Reset I Master Clock Input I/O Reference Clock O Backplane Clock Output UTOPIA L2/3 or POS-PHY L2/3 or SPI-3 System Interface I Transmit System Clock I Transmit Address [4:0]
I I I I O I
E9 F9 B10 A10 C10 D10 E10 F10 B11 A11 C11 D11 B12 M3 P10 R10 T10 N10 M10 R8 C9 A9 D9 D16 A13. D12 B13 E11 A12 M12 L14 M14 R13 T13 P13 D13 E12 N13 L12 M13 L13 R16 T16 T14 R15 C12 C13 C15
I
Transmit Data [15:0]
I I Oz
Transmit Parity Transmit Enable Transmit Direct cell/packet Available [1] / Polled cell/packet Available (tri-state)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Pin # Name TDXA[4] TDXA[3] TDXA[2] TSOX TSPA TEOP TSX TMOD TERR RSCLK RADR[4] RADR[3] RADR[2] RADR[1] RADR[0] RDATA[15] RDATA[14] RDATA[13] RDATA[12] RDATA[11] RDATA[10] RDATA[9] RDATA[8] RDATA[7] RDATA[6] RDATA[5] RDATA[4] RDATA[3] RDATA[2] RDATA[1] RDATA[0] RPAR REN RDXA[1] / RPXA / RSX RDXA[4] RDXA[3] RDXA[2] RSOX REOP RVAL RMOD RERR GTEST1 GTEST2 TTEST3 TTEST2 TTEST1 RTEST3 RTEST2 RTEST1 SCAN_EN SCAN_MODE Type O I Oz I I I I I I Function Transmit Direct cell/packet Available [4:2] Transmit Start Of cell/packet Transmit Selected Packet Available Transmit End Of Packet Transmit Start of Transfer Transmit packet data Modulus Transmit packet Error Receive System Clock Receive Address [4:0] Port 4 Port Port 3 2 F11 B16 C14 P12 C16 T12 R12 F14 N12 H14 J12 K13 P16 P15 N15 H13 H12 M15 N16 G13 K15 L15 L16 M16 J13 J14 J16 K16 G16 H16 F16 F15 D14 D15 A16 A14 B15 F12 G15 E15 F13 E13 D4 E4 M8 N8 L9 P7 T7 R7 P8 T8 21 of 362 Port 1
Oz
Receive Data [15:0] (tri-state)
Oz I Oz O Oz Oz Oz Oz Oz I I I I
Receive Parity (active low tri-state) Receive Enable (active low) Receive Direct cell/packet Available [1] / Polled cell/packet Available / Start of Transfer (tri-state) Receive Direct cell/packet Available [4:2] Receive Start Of cell/packet (tri-state) Receive End Of Packet Receive packet data Valid Receive packet data Modulus Receive packet Error TEST Global Test Transmit Test Receive Test Scan Enable Scan Mode
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Pin # Name Type Function POWER Ground, 0 Volt potential Digital 3.3V Analog 3.3V for receive LIU on port n Analog 3.3V for transmit LIU on port n Analog 3.3V for CLAD Analog Gnd for receive LIU Analog Gnd for transmit LIU Analog Gnd for CLAD No Connects No Connect Note: Do not connect any signal to these balls, leave unconnected. Port 4 Port 3 Port 2 Port 1
VSS VDD AVDDRn AVDDTn AVDDC AVSSRn AVSSTn AVSSC NC
PWR PWR PWR PWR PWR PWR PWR PWR NC
E14, K8, K7, K5, K6, J5, J9, J6, K11, K12, K10, K9, J10, J8, J11 G6, G7, H5, G5, H9, G12, H6, G11,G10, H10, G9, J7, G8, H11 D1, E1, M1, N1 B1, G1, K1, R1 H7 D2, E2, M2, N2 B2, G2, K2, R2 H8 A15, B14, E16, G14, H15, J15, K14, R14, T15
5.2
Detailed Pin List
Table 5-2 Pin Descriptions
Signal Name I/O Description
Backplane TDM Signals RSER[4:1] O RCLKO[4:1] RSYNC[4:1] RM_RFSYNC [4:1] O O O
RCHMRK[4:1]
O
TSERO[4:1]
O
Receive Serial Data This output is the recovered raw data stream containing all overhead T1, E1 or J1 bits. This signal is updated on the rising edge of RCLK output. Receive Clock Out This output is the recovered network clock under normal conditions. During loss of signal conditions this clock is derived from the scaled signal at MCLK. Receive Sync An output sync pulse indicating the frame or multiframe boundaries in the data at RSER. Receive Multiframe or Frame Sync An output sync pulse indicating the frame or multiframe boundaries in the data at RSER in normal operation. When the high-speed bus is enabled, this output will indicate frame boundaries associated with the high-speed, multiplexed TDM bus operation. Receive Channel Marker This output signal is user definable to be a cell/packet-mapping indicator in which it is high during channels mapped to the cell/packet interface or a channel clock. As a cell/packet mapping indicator this signal will be high during channels mapped to the cell/packet interface and can be used to de-multiplex non cell/packet data from the data stream at RSER. As a channel clock the user can program this output to pulse during the LSB of all channel times or produce a gated clock during any combinations of channels in both 64kbps or 56 kbps mode. RCHMRK is updated on the rising edge of RCLK. Transmit Serial Data Out This is the output of the transmit cell/packet interface. In a pure cell/packet operation this pin can be connected to TSERI. This signal along with TCHMRK and TSERI can be used to multiplex TDM data with the cell/packet data. TSERO is updated on the rising edge of TCLK 22 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver TSERI[4:1] I Transmit Serial Data In This is the input to the transmit framer. In a pure cell/packet operation this pin can be connected to TSERO. This signal along with TCHMRK and TSERO can be used to multiplex TDM data with the cell/packet data. This signal is sampled on the falling edge of TCLK. Transmit Clock A 1.544 MHz or a 2.048MHz primary transmit clock. Under normal operation this signal clocks data through the transceiver onto the network. Transmit Sync This signal can be defined as an output or input in either a frame or multiframe format. As an output, it is updated on the rising edge of TCLK. If the transmit synchronizer is enabled, this output will be synchronous to the embedded framing overhead in the signal present at TSERI. If there is no embedded framing overhead in the TSERI signal (the transmit synchronizer is disabled), TSYNC will assume an arbitrary alignment and it is up to the user to align data at TSERI with TSYNC. As an input, the user can force the transmit framer to align to the data present at TSERI. If the data at TSERI contains complete framing overhead the user can program the transmit framer to pass the overhead bits unmolested. Otherwise the transmit framer will calculate and insert all the appropriate overhead depending on the operational mode selected. TSYNC is sampled on the falling edge of TCLK. TCHMRK[4:1] O Transmit Channel Marker This output signal is user definable to be a cell/packet-mapping indicator in which it is high during channels mapped to the cell/packet interface or a channel clock. As a cell/packet mapping indicator this signal will be high during channels mapped to the cell/packet interface and can be used to multiplex non cell/packet data with the data stream at TSERO. As a channel clock the user can program this output to pulse during the LSB of all channel times or produce a gated clock during any combinations of channels in both 64kbps or 56 kbps mode. TCHMRK is updated on the rising edge of TCLK.
TCLK[4:1]
I
TSYNC[4:1]
I/O
Backplane HS TDM Signals HRDATA O High Speed Bus Receive Data This output is the frame interleaved received data bus. This signal is updated on the rising edge of HSYSCLK. HTDATA I High Speed Bus Transmit Data This input is the frame interleaved transmit data bus. This signal is sampled on the falling edge of HSYSCLK. HSYSCLK I High Speed Bus System Clock A 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock used to drive the high speed multiplexed bus. HTSIG I High Speed Bus Transmit Signaling TDM Stream Input for the TDM signaling data to be inserted into the transmit data stream. This signal is sampled on the falling edge of HSYSCLK. HRSIG O High Speed Bus Receive Signaling TDM Stream This output is the extracted TDM signaling data from the receive data stream. This signal is updated on the rising edge of HSYSCLK. HSSYNC I/O High Speed Bus System Sync This input establishes the frame boundary for the multiplexed high-speed bus. This signal is sampled on the falling edge of HSYSCLK.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Status Signals ROCD[4:1] RLCD[4:1] RLOF/LOTC[4:1] RLOS[4:1]
O O O O
Receive Out of Cell Delineation This output will be high when the cell processor is in an Out of Cell Delineation state. Receive Loss of Cell Delineation This output will be high when the cell processor has been in an Out of Cell Delineation condition for a programmed number of cells. Receive Loss Of Frame / Loss Of Transmit Clock This output is user selectable to be high during either a loss of synchronization or loss of transmit clock. Receive Loss Of Signal This output will be high during a loss of signal at RTIP and RRING.
Microcontroller Interface Signals ADDR[12:0] I Address Bus ADDR[12:0] DATA[7:0] I/O Data Bus DATA[7:0] I Chip Select CS CS: Must be low to read or write to the device. CS is an active-low signal. This signal is used for both the parallel port and the serial port modes. I Write Input(Read/Write) WR(R/W) I Read Input-Data Strobe RD(DS) BTS I Bus Type Select This bit selects the processor interface mode of operation. 0 = Multiplexed 1 = Non-multiplexed INT O Interrupt INT: Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output. JTAG Signals JTRST
I
JTCLK JTMS JTDI JTDO
I I I O
JTAG Reset (active low) This input forces the JTAG controller logic into the reset state and forces the JTDO pin into high impedance when low. This pin should be low while power is applied and set high after the power is stable. The pin can be driven high or low for normal operation, but must be high for JTAG operation. JTAG Clock This clock input is typically a low frequency (less than 10 MHz) 50% duty cycle clock signal. JTAG Mode Select (with pullup) This input signal is used to control the JTAG controller state machine and is sampled on the rising edge of JTCLK. JTAG Data Input (with pullup) This input signal is used to input data into the register that is enabled by the JTAG controller state machine and is sampled on the rising edge of JTCLK. JTAG Data Output This output signal is the output of an internal scan shift register enabled by the JTAG controller state machine and is updated on the falling edge of JTCLK. The pin is in the high impedance mode when a register is not selected or when the JTRST signal is high. The pin goes into and exits the high impedance mode after the falling edge of JTCLK
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Network Interface Signals RRING[4:1] I Receive Ring Analog input for clock recovery circuitry. This pin connects via a 1:1 transformer to the network. See Line Interface Unit for details. RTIP[4:1] I Receive Tip Analog input for clock recovery circuitry. This pin connects via a 1:1 transformer to the network. See Line Interface Unit for details. TRING[4:1] O Transmit Ring Analog line driver output. This pin connects via a 1:2 step-up transformer to the network. See Line Interface Unit for details. STRING[4:1] O Secondary Transmit Ring Analog line driver output. Internally connected to TRING. TTIP[4:1] O Transmit Tip Analog line driver output. This pin connects via a 1:2 step-up transformer to the network. See Line Interface Unit for details. STTIP[4:1] O Secondary Transmit Tip Analog line driver output. Internally connected to TTIP. TXENABLE I Transmit High Impedance Enable When high, TTIP and TRING will be placed into a high impedance state. Backplane UTOPIA/POS-PHY Signals RSCLK I Receive System Interface Clock This signal is used to sample or update the other receive system interface signals. RSCLK has a maximum frequency of 52 MHz. RDAT[15:0] O Receive System Interface Data Bus This 16-bit data bus is used to transfer cell/packet data to the ATM/Link layer device. This bus is updated on the rising edge of RSCLK. In 16-bit mode, RDAT15 is the MSB, RDAT0 is the LSB In 8-bit mode, RDAT7 is the MSB, RDAT0 is the LSB, and RDAT[15:8] are held low. Receive System Interface Parity This signal indicates the parity on the data bus. This signal is updated on the rising edge of RSCLK. Receive System Interface Address Bus This 5-bit address bus is used by the ATM/Link layer device to select a specific port. RADR4 is the MSB and RADR0 is the LSB. This bus is sampled on the rising edge of RSCLK. In POS-PHY Level 3 mode, this bus is ignored. Receive System Interface Enable This signal is used by the ATM/Link device to control the transfer of cell/packet data on the RDAT bus. If REN is high, no transfer occurs. If REN is low, a transfer occurs. This signal is sampled on the rising edge of RSCLK.
RPAR RADR[4:0]
O I
REN
I
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver RDXA[4:2] O Receive System Interface Direct Cell/Packet Available This signal is used to indicate when the associated port can send data to the ATM/Link layer device. This signal is updated on the rising edge of RSCLK. In UTOPIA mode, RDXA goes high when the associated port has more than a programmable number of ATM cells ready for transfer ("almost empty" level). RDXA goes low when the associated port does not have a complete ATM cell ready for transfer. In POS-PHY Level 2 mode, RDXA goes high when the associated port contains more data than the "almost empty" level or has an end of packet ready for transfer. RDXA goes low when the associated port does not have an end of packet ready for transfer and is "almost empty". In POS-PHY Level 3 mode, this signal is held low. Receive Direct cell/packet Available [1] / Polled cell/packet Available / Start of Transfer (tri-state) This signal is tri-state when global reset is applied. RDXA[1]: This signal is active in UTOPIA L2, UTOPIA L3 or POS-PHY L2 modes when direct status mode is selected. It is used to indicate when port 1 can send data to the ATM/Link layer device. This signal is updated on the rising edge of RSCLK. In UTOPIA L2 or UTOPIA L3 modes, RDXA goes high when port 1 has more than a programmable number of ATM cells ready for transfer ("almost empty" level). RDXA goes low when the associated port does not have a complete ATM cell ready for transfer. In POS-PHY L2 mode, RDXA goes high when port 1 contains more data than the "almost empty" level or has an end of packet ready for transfer. RDXA goes low when the associated port does not have an end of packet ready for transfer and is "almost empty". RPXA: (Reset default) This signal is active in UTOPIA L2, UTOPIA L3, or POSPHY L2 modes when polled status mode is selected. It is used to indicate when the polled port, as selected by RADR[4:0], can send data to the ATM/Link layer device. This signal is updated on the rising edge of RSCLK. In UTOPIA L2 or UTOPIA L3 modes, RPXA goes high when the polled port has more than a programmable number of ATM cells ready for transfer ("almost empty" level). RPXA goes low when the polled port does not have a complete ATM cell ready for transfer. In POS-PHY L2 mode, RPXA goes high when the polled port contains more data than the "almost empty" level or has an end of packet ready for transfer. RPXA goes low when the port does not have an end of packet ready for transfer and is "almost empty". In UTOPIA L2 (reset default) or POS-PHY L2 modes, this signal is driven when one of the ports is being polled, and is tri-stated when none of the ports is being polled or when data path reset is active. In UTOPIA L3 mode this signal is driven. RSX: This signal is active in POS-PHY L3 modes and indicates the start of a data transfer. This signal is updated on the rising edge of RSCLK. RSX goes high immediately before the start of data transfer to indicate that the inband port address is present on RDATA. RSX goes high when the value of RDATA is the address of the receive port from which data is to be transferred. When RSX goes low, all subsequent transfers will be from the port specified by the in-band address. When RSX is high, RVAL must be low. This signal is always driven in POS-PHY L3 mode. Receive System Interface Start Of Cell/Packet This signal is used to indicate the first transfer of a cell/packet. This signal is updated on the rising edge of RSCLK. In UTOPIA mode, RSOX is used to indicate the first transfer of a cell. In POS-PHY mode, RSOX is used to indicate the first transfer of a packet.
RDXA[1] / RPXA / RSX
O
RSOX
O
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver REOP O Receive System Interface End Of Packet This signal is used to indicate the last transfer of a packet. This signal is updated on the rising edge of RSCLK. In UTOPIA mode, this signal is held low. Receive System Interface Data Valid This signal is used to indicate the validity of a receive data transfer. When RVAL is high, the receive data bus (RDAT, RPAR, RSOX, REOP, RMOD, and RERR) is valid and a packet data transfer occurs. When RVAL is low, the receive data bus is invalid and a data transfer does not occurs. This signal is updated on the rising edge of RSCLK. RVAL goes high when a port is selected for packet data transfer and the port has a programmable size block of data or an end of packet ready for transfer. In POSPHY Level 2 mode, RVAL goes low if the selected port is empty, at the end of a packet, or when REN is deasserted. Once RVAL goes low, it will remain low until REN is deasserted. In POS-PHY Level 3 mode, RVAL goes low if the selected port is empty or at the end of a packet if the minimum deassertion time is greater than zero. RVAL will remain deasserted for the programmable minimum deassertion time. In UTOPIA mode, this signal is held low. Receive System Interface Data Bus Modulus This signal is used to indicate the number of valid bytes on the RDAT bus. RMOD = 0 RMOD = 1 RDAT[15:0] valid RDAT[15:8] valid
RVAL
O
RMOD
O
RERR
O
TSCLK TDAT[15:0]
I I
TPAR TADR[4:0]
I I
TEN
I
This signal is updated on the rising edge of RSCLK. RMOD is only valid when REOP is high. In UTOPIA or 8-bit POS-PHY mode, this signal is held low. Receive System Interface Packet Error This signal is used to indicate that the current packet is errored. When RERR is high, the current packet should be aborted. This signal is updated on the rising edge of RSCLK. RERR is only valid when REOP is high. In UTOPIA mode, this signal is held low. Transmit System Interface Clock This signal is used to sample or update the other transmit system interface signals. TSCLK has a maximum frequency of 52 MHz. Transmit System Interface Data Bus This 16-bit data bus is used to transfer cell/packet data from the ATM/Link layer device. This bus is sampled on the rising edge of TSCLK. In 16-bit mode, TDAT15 is the MSB, TDAT0 is the LSB. In 8-bit mode, TDAT7 is the MSB, TDAT0 is the LSB, and TDAT[15:8] are held low. Transmit System Interface Parity This signal indicates the parity on the data bus. This signal is sampled on the rising edge of TSCLK. Transmit System Interface Address Bus This 5-bit address bus is used by the ATM/Link layer device to select a specific port. TADR7 is the MSB and TADR0 is the LSB. This bus is sampled on the rising edge of TSCLK. Transmit System Interface Enable This signal is used by the ATM/Link device to control the transfer of cell/packet data on the TDAT bus. If TEN is high, no transfer occurs. If TEN is low, a transfer occurs. This signal is sampled on the rising edge of TSCLK.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver TDXA[4: 2] O Transmit System Interface Direct Cell/Packet Available This signal is used to indicate when the associated port can accept data from the ATM/Link layer device. This signal is updated on the rising edge of TSCLK. In UTOPIA mode, TDXA goes high when the associated port can accept the transfer of more than a programmable number of ATM cells. TDXA goes low when the associated port cannot accept the transfer of a complete ATM cell. In POS-PHY mode, TDXA goes high when the associated port can store more data than the "almost full" level. TDXA goes low when the associated port is full. Transmit Direct cell/packet Available [1] / Polled cell/packet Available (tri-state) This signal is tri-state when global reset is applied. TDXA[1]: When direct status mode is selected, this signal is used to indicate when port 1 can accept data from the ATM/Link layer device. This signal is updated on the rising edge of TSCLK. In UTOPIA L2 or UTOPIA L3 modes, TDXA goes high when port 1 can accept the transfer of more than a programmable number of ATM cells. TDXA goes low when port 1 cannot accept the transfer of a complete ATM cell. In POS-PHY L2 or POS-PHY L3 modes, TDXA goes high when port 1 can store more data than the "almost full" level. TDXA goes low when port 1 is full. TPXA: (reset default) When polled status mode is selected, this signal is used to indicate when the polled port, as selected by TADR[4:0], can accept data from the ATM/Link layer device. This signal is updated on the rising edge of TSCLK. In UTOPIA L2 or UTOPIA L3 modes, TPXA goes high when the polled port can accept the transfer of more than a programmable number of ATM cells. TPXA goes low when the polled port cannot accept the transfer of a complete ATM cell. In POS-PHY L2 or POS-PHY L3 modes, TPXA goes high when the polled port can store more data than the "almost full" level. TPXA goes low when the polled port is full. In UTOPIA L2 (reset default) or POS-PHY L2 modes, this signal is driven when one of the ports is being polled, and is tri-stated when none of the ports is being polled or when data path reset is active. In UTOPIA L3 or POS-PHY L3 modes, this signal is driven. Note: Polled status mode and direct status mode is selected by the GCR1.DIREN bit. Transmit System Interface Start Of Cell/Packet This signal is used to indicate the first transfer of a cell/packet. This signal is sampled on the rising edge of TSCLK. In UTOPIA mode, TSOX indicates the first transfer of a cell. In POS-PHY mode, TSOX indicates the first transfer of a packet. Transmit System Interface Selected Packet Available This signal is used to indicate the selected port can accept data from the Link layer device. TSPA goes high when a port is selected for transfer and it can accept more data than the "almost full" level. TSPA goes low when the selected port is "full" or no port is selected. This signal is updated on the rising edge of TSCLK. In UTOPIA mode, this signal is held low. Transmit System Interface End Of Packet This signal is used to indicate the last transfer of a packet. This signal is sampled on the rising edge of TSCLK. In UTOPIA mode, this signal is ignored. Transmit System Interface Start of Transfer This signal indicates the start of a data transfer. TSX goes high goes high immediately before the start of data transfer to indicate that the in-band port address is present on TDAT. TSX goes high when the value of TDAT is the address of the transmit port to which data is to be transferred. When TSX goes low, all subsequent transfers will be to the port specified by the in-band address. This signal is sampled on the rising edge of TSCLK. TSX is only valid when TEN is high. In UTOPIA or POS-PHY Level 2 mode, this signal is ignored.
TDXA[1] / TPXA
O
TSOX
I
TSPA
O
TEOP
I
TSX
I
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver TMOD I Transmit System Interface Data Bus Modulus This signal indicates the number of valid bytes on the TDAT bus. TMOD = 0 TMOD = 1 TDAT[15:0] valid TDAT[15:8] valid
TERR
I
This signal is sampled on the rising edge of TSCLK. TMOD is only valid when TEOP is high. In UTOPIA or 8-bit POS-PHY mode, this signal is ignored. Transmit System Interface Packet Error This signal indicates that the current packet is errored. When TERR is high, the current packet should be aborted. This signal is sampled on the rising edge of TSCLK. TERR is only valid when TEOP is high. In UTOPIA mode, this signal is ignored.
Clock Signals
RESET
MCLK
BPCLK
REFCLK
Reset (active low) This signal resets all the internal processor registers and logic when low. This pin should be low while power is applied and set high after the power is stable. This is an asynchronous input. I Master Clock Input A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26556 in T1only operation a 1.544MHz (50ppm) clock source can be used. O Backplane Clock This output clock is generated using the REFCLK signal as its source or one of the RCLKO[4:1] signals as its source and can be a 2.048 MHz, 4.096 MHz, or 8.192 MHz. This clock can be externally wired to HSYSCLK. I/O Reference Clock This clock is used as the reference source for the BPCLK either as an output or as an input. As an input, the input frequency must be either 1.544 MHz or 2.048 MHz. The mode of operation is controlled by the GCCR Register.
I
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6 DEVICE CONFIGURATION
A typical, high-level device configuration scenario is shown below. There are many more aspects to setting up the device as described in this data sheet. This is intended to give the user a general procedure for setting up the DS26556. 1) Configure Port Network Interface Mode (per-port): This step determines how each port will interface to the physical network i) T1 (a) ESF (b) D4 ii) E1 (a) FAS only (b) FAS + CRC4 (c) FAS + CAS (d) FAS + CRC4 + CAS iii) J1 (a) ESF (b) D4 2) Configure Cell/Packet Interface Mode (global): This step places the Cell/Packet interface into the ATM Cell mode or IP Packet mode. This selection is global to all ports. i) Cell or Packet mode (1) Cell (2) Packet ii) Select Cell/Packet backplane bus configuration (1) 8 bits (2) 16 bits 3) Configure Port Backplane Interface (per-port): This step determines how each port will be interfaced to the three backplane types available (Cell/Packet, TDM, High Speed Multiplexed TDM). i) Pure Cell/packet (a) Map all channels to Cell/Packet Interface ii) Fractional Cell/Packet (a) Select channels to be mapped to Cell/Packet interface iii) Mixed TDM and Cell/Packet (a) Select channels to be mapped to Cell/Packet interface (b) Channels not mapped to Cell/Packet interface are available on TDM port. NOTE: All channels are actually available at the TDM ports. Signals at RCHMRK and TCHMRK pins indicate mapping status of each channel. iv) High Speed Multiplexed TDM Bus 4) Configure Controller Interface i) Enable appropriate interrupts
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7 FUNCTIONAL PIN TIMING
7.1 Receiver Functional Timing Diagrams
Figure 7-1 Receive TDM Signals
CHANNEL RCLK RSER RSYNC RCHMRK1 RCHMRK2 RCHMRK3
Notes: 1 RCHMRK in cell/packet mapping indicator mode 2 RCHMRK in channel marking mode 3 RCHMRK in gapped clock mode
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 7-2 Receive TDM Signals, Details
CHANNEL 1 RCLK RSER RSYNC RCHMRK1 RCHMRK2 RCHMRK3 LSB MSB LSB MSB CHANNEL 2
Notes: 1 RCHMRK in cell/packet mapping indicator mode 2 RCHMRK in channel marking mode 3 RCHMRK in gapped clock mode
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7.2
Transmitter Functional Timing Diagrams
Figure 7-3 Transmit TDM Signals
CHANNEL TCLK TSERI TSYNC TCHMRK1 TCHMRK2 TCHMRK3 Notes: 1 TCHMRK in cell/packet mapping indicator mode 2 TCHMRK in channel marking mode 3 TCHMRK in gapped clock mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 7-4 Transmit TDM Signals, Details
CHANNEL 1 TCLK TSERI TSYNC TCHMRK1 TCHMRK2 TCHMRK3 Notes: 1 TCHMRK in cell/packet mapping indicator mode 2 TCHMRK in channel marking mode 3 TCHMRK in gapped clock mode LSB MSB LSB MSB CHANNEL 2
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-5 Two Port High Speed TDM Bus
PORT 2 CHANNELS 1-32 PORT 1 CHANNELS 1-32 PORT 2 CHANNELS 1-32 PORT 1 CHANNELS 1-32 PORT 2 CHANNELS 1-32
HSSYNC HTDATA HRDATA HTSIG HRSIG
PORT 2 CHANNELS 1-32
PORT 1 CHANNELS 1-32
BIT DETAIL HSYSCLK HSSYNC
PORT 2, CHANNEL 32 PORT 1, CHANNEL 1
LSB MSB LSB MSB
PORT 1, CHANNEL 2
LSB
HRDATA / HTDATA
PORT 2, CHANNEL 32
PORT 1, CHANNEL 1
A B C/A D/B
PORT 1, CHANNEL 2
A B C/A D/B
HRSIG / HTSIG
A
B
C/A D/B
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-6 Four Port High Speed TDM Bus
PORT 4 CHANNELS 1-32 PORT 1 CHANNELS 1-32 PORT 2 CHANNELS 1-32 PORT 3 CHANNELS 1-32 PORT 4 CHANNELS 1-32
HSSYNC HTDATA HRDATA HTSIG HRSIG
PORT 4 CHANNELS 1-32
PORT 1 CHANNELS 1-32
BIT DETAIL HSYSCLK HSSYNC
PORT 4, CHANNEL 32 PORT 1, CHANNEL 1
LSB MSB LSB MSB
PORT 1, CHANNEL 2
LSB
HRDATA / HTDATA
PORT4, CHANNEL 32
PORT 1, CHANNEL 1
A B C/A D/B
PORT 1, CHANNEL 2
A B C/A D/B
HRSIG / HTSIG
A
B
C/A D/B
7.3
7.3.1
UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing
UTOPIA Level 2 Functional Timing
Figure 7-7 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device places address `00h' on the address bus (which is mapped to Port 1). PHY device '1' (Port 1) indicates to the ATM device that it can accept cell data by asserting TDXA[1]. On clock edge 4, the ATM device selects PHY device '1'. On clock edge 5, the ATM device starts a cell transfer to PHY device '1' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA.. On clock edge 13, PHY device `2' asserts TDXA[2] to indicate to the ATM device that it is ready to accept cell data. On clock edge 15, PHY device '1' indicates that it cannot accept the transfer of a complete cell by deasserting TDXA[1]. On clock edge 16, the ATM device deselects PHY device '1' and selects PHY device '2' by deasserting TEN and placing PHY device '2's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY device '2' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-7 UTOPIA Level 2 Transmit Cell Transfer Direct Mode
TCLK TADR TDXA[1] TDXA[2] TDXA[3] TDXA[4] TEN TDATA TSOX
Transfer Cell To: PORT 1 PORT 2 H1 H2 H3 00h 01h
...
8
P42
P43
P44
P45
P46
P47
P48
H1
H2
H3
H4
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
20
Figure 7-8 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device places address `00h' on the address bus (which is mapped to Port 1). PHY device '1' (Port 1) indicates to the ATM device that it has a complete cell to send by asserting RDXA[1]. On clock edge 4, the ATM device selects PHY device '1'. On clock edge 5, the ATM device asserts REN. On clock edge 6, the PHY device `1' starts a cell transfer to the ATM device by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 7, the PHY device deasserts RSOX as it continues to place additional bytes of the cell on RDATA. On clock edge 13, PHY device `2' asserts RDXA[2] to indicate to the ATM device that it is ready to send a cell. On clock edge 15, PHY device '1' indicates that it cannot transfer a complete cell by deasserting RDXA[1]. On clock edge 16, the ATM device deselects PHY device '1' and selects PHY device '2' by deasserting REN and placing PHY device '2's address on RADR. On clock edge 17, the ATM device asserts REN. On clock edge 18, PHY device `2' (Port 2) starts the transfer of a cell to the ATM device by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the PHY device deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 7-8 UTOPIA Level 2 Receive Cell Transfer Direct Mode
RSCLK RADR RDXA[1] RDXA[2] RDXA[3] RDXA[4] REN RDATA RSOX
Transfer Cell From: PORT 1 PORT 2 H1 H2 00h 01h
... H3
8 9
P42
P43
P44
P45
P46
P47
P48
H1
H2
H3
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Figure 7-9 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it can accept cell data by asserting TPXA. On clock edge 4, the ATM device selects PHY device 'N'. On clock edge 5, the ATM device starts a cell transfer to PHY device 'N' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA. On clock edge 6, the ATM device also polls PHY device 'O'. On clock edge 7, PHY device 'O' indicates that it can accept the transfer of a complete cell. On clock edge 14, the ATM device polls PHY device 'N'. On clock edge 15, PHY device 'N' indicates that it cannot accept the transfer of a complete cell. On clock edge 16, the ATM device deselects PHY device 'N' and selects PHY device 'O' by deasserting TEN and placing PHY device 'O's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY device 'O' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA.
Figure 7-9 UTOPIA Level 2 Transmit Multiple Cell Transfer Polled Mode
TCLK TADR TPXA TEN TDATA TSOX Transfer Cell To: 1 2 3 4 5 6 7 8 9 N 10 O 11 12 13 14 15 16 17 18 19 20 H1 H2 H3 ... P42 P43 P44 P45 P46 P47 P48 H1 H2 H3 H4 M 1F M N 1F N N 1F N O 1F O ... 1F P L 1F M L 1F M N 1F N O 1F O P 1F P L
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Figure 7-10 shows a multidevice receive-interface multiple cell transfer from different PHY devices. On clock edge 2, the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock edge 4, the ATM device selects PHY device 'N'. On clock edge 5, the ATM device asserts REN. On clock edge 6, PHY device 'N' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 7, PHY device 'N' deasserts RSOX as it continues to place additional bytes of the cell on RDATA. On clock edge 12, the ATM device polls PHY device 'O'. On clock edge 13, PHY device 'O' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock edge 16, the ATM device deselects PHY device 'N' and selects PHY device 'O' by deasserting REN and placing PHY device 'O's address on RADR. On clock edge 17, the ATM device asserts REN and PHY device 'N' stops transferring cell data and tri-states its RDATA and RSOX outputs. On clock edge 18, PHY device 'O' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY device 'O' deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 7-10 UTOPIA Level 2 Receive Multiple Cell Transfer Polled Mode
RCLK RADR M RPXA REN RDATA RSOX
Transfer Cell From: N O H1 H2 1F M N 1F N N 1F N O 1F O
... ...
8
1F L
M
1F M
O
1F O
P
1F P
O
1F O
N
1F N
P
P41 P42 P43 P44 P45 P46 P47 P48
H1
H2
H3
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
20
Figure 7-11 shows a multidevice receive-interface unexpected multiple cell transfer. Prior to clock edge 1, the cell transfer was started. On clock edge 4, since no other PHY device has a cell ready for transfer, the ATM device assumes another cell transfer from PHY device 'N' and leaves REN asserted. On clock edge 5, PHY device 'N' stops transferring cell data and indicates that it does not have another cell ready for transfer by not asserting RSOX. On clock edge 6, the ATM device deasserts REN to end the cell transfer process. At the same time, PHY device 'N' indicates to the ATM device that it now has a complete cell ready for transfer by placing the first byte of cell data on RDAT, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 7, PHY device 'N' tristates its RDAT and RSOX outputs because REN is deasserted. On clock edge 8, the ATM device selects PHY device 'N'. On clock edge 9, the ATM device asserts REN. On clock edge 10, PHY device 'N' continues the cell transfer by placing the second byte of cell data on RDAT, and deasserting RSOX.
Figure 7-11 UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer
RCLK RADR RPXA REN* RDAT RSOX
Transfer Cell From: N P45 P46 P47 P48 X H1 H2 H3 H4 P1 P2 P3 P4 P5 P6 P7 P8 L 1F L M 1F M N 1F N O 1F O N 1F N P 1F P L 1F L M 1F M O 1F O P 1F P L
N N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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7.3.2
UTOPIA Level 3 Functional Timing
Figure 7-12 shows a multiport transmit-interface multiple cell transfer to different PHY devices. PHY port '1', `3', `4' indicate to the ATM device that they can accept cell data by asserting the TDXA[n]. On clock edge 2, the ATM device selects PHY port '1' by putting address `00h' on the address bus. On clock edge 5, the ATM device starts a cell transfer to PHY port '1' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA. On clock edge 13, PHY port `2' asserts TDXA[2] to indicate it is ready to accept a cell. On clock edge 15, PHY port `1' deasserts TDXA[1] to indicate to the ATM device that it does not have the availability to receive another complete cell. On clock edge 16, the ATM device selects PHY port '2' by deasserting TEN and placing PHY port '2's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY port '2' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA.
Figure 7-12 UTOPIA Level 3 Transmit Multiple Cell Transfer Direct Mode
TSCLK TADR TDXA[1] TDXA[2] TDXA[3] TDXA[4] TEN TDATA TSOX
Transfer Cell To: PORT 1 PORT 2 H1 H2 H3 00h 01h
...
8
P42
P43
P44
P45
P46
P47
P48
H1
H2
H3
H4
1
2
3
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Figure 7-13 shows a multiport transmit-interface multiple cell transfer to different PHY devices. On clock edge 1, the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it can accept cell data by asserting TPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device starts a cell transfer to PHY port 'N' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 7, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA. On clock edge 11, the ATM device polls PHY port 'M'. On clock edge 12, the ATM device polls PHY port 'N'. On clock edge 13, PHY port 'M' indicates that it can accept the transfer of a complete cell. On clock edge 14, PHY port 'N' indicates that it cannot accept the transfer of a complete cell. On clock edge 16, the ATM device deselects PHY port 'N' and selects PHY port 'M' by deasserting TEN and placing PHY port 'M's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY port 'M' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA.
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Figure 7-13 UTOPIA Level 3 Transmit Multiple Cell Transfer Polled Mode
TCLK TADR TPXA TEN TDATA TSOX Transfer Cell To:
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 M 18 19 20 X X X X X X H1 H2 H3 ... P43 P44 P45 P46 P47 P48 X H1 H2 H3 P1 M K N L O M P N Q O N P R Q J X K R ... ... L J M K N L O M P N Q O M P R Q J X K R L J
Figure 7-14 shows a multiport receive-interface multiple cell transfer from different PHY ports. On clock edge 3, PHY port 'N' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device indicates to PHY port 'N' that it is ready to accept a complete cell transfer by asserting REN. On clock edge 8, PHY port 'N' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 9, PHY port 'N' deasserts RSOX as it continues to place additional bytes of the cell on RDAT. On clock edge 11, the ATM device polls PHY device 'N'. On clock edge 12, PHY port 'M' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock edge 12, PHY port 'N' indicates to the ATM device that it does not have a complete cell ready for transfer by deasserting RPXA. On clock edge 15, the ATM device deselects PHY port 'N' and selects PHY port 'M' by deasserting REN and placing PHY port 'M's address on RADR. On clock edge 16, the ATM device asserts REN. On clock edge 17, PHY port 'N' stops transferring cell data. On clock edge 18, PHY port 'M' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY port 'M' deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-14 UTOPIA Level 3 Receive Multiple Cell Transfer Direct Mode
RSCLK RADR RDXA[1] RDXA[2] RDXA[3] RDXA[4] REN RDATA RSOX
Transfer Cell From: PORT 1 PORT 2 H1 H2 H3 00h 01h
... P42
9 10
P43
P44
P45
P46
P47
P48
H1
H2
H3
1
2
3
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5
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11
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Figure 7-15 shows a multiport receive-interface multiple cell transfer from different PHY ports. On clock edge 1, the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device indicates to PHY port 'N' that it is ready to accept a complete cell transfer by asserting REN. On clock edge 8, PHY port 'N' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 9, PHY port 'N' deasserts RSOX as it continues to place additional bytes of the cell on RDAT. On clock edge 11, the ATM device polls PHY device 'N'. On clock edge 12, PHY port 'M' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock edge 12, PHY port 'N' indicates to the ATM device that it does not have a complete cell ready for transfer by deasserting RPXA. On clock edge 15, the ATM device deselects PHY port 'N' and selects PHY port 'M' by deasserting REN and placing PHY port 'M's address on RADR. On clock edge 16, the ATM device asserts REN. On clock edge 17, PHY port 'N' stops transferring cell data. On clock edge 18, PHY port 'M' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY port 'M' deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 7-15 UTOPIA Level 3 Receive Multiple Cell Transfer Polled Mode
RCLK RADR M RPXA K REN RDAT RSOX Transfer Cell From:
X X X X X X X X H1 H2 N L O M P N Q O N P R Q J N K R L J
... ... ...
10
N L
O M
P N
Q O
M P
R Q
J M
K R
L J
M K
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P44
P45
P46
P47
P48
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H2
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M
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7.3.3
POS-PHY Level 2 Functional Timing
Figure 7-16 shows a multidevice transmit interface in byte transfer mode multiple packet transfer to different PHY ports. Prior to clock edge 1, the POS device started a packet transfer to PHY port '1'. On clock edge 2, PHY port '1' deasserts its TDXA to indicate to the POS device that it cannot accept any more data transfers. On clock edge 3, the POS device stops the packet transfer to PHY port '1', and starts a packet transfer to PHY port '2' by leaving TEN asserted, placing PHY port '2's address on TADR, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 7, PHY port '2' deasserts its TDXA to indicate to the POS device that it cannot accept any more data transfers. On clock edge 8, the POS device stops the packet transfer to PHY port '2', and resumes a packet transfer to PHY port '3'. On clock edge 12, PHY port '2' indicates to the POS device that it can accept a block of packet data by asserting its TDXA. Also, the POS device indicates it is transferring the last byte of packet data by asserting TEOP. On clock edge 13, the POS device ends the packet transfer to PHY port '3', and starts a packet transfer to PHY port '4'. On clock edge 15, PHY port '1' indicates to the POS device that it can accept a block of packet data. On clock edge 17, PHY port '4' deasserts its TDXA to indicate to the POS device that it cannot accept any more data transfers. On clock edge 18, the POS device stops the packet transfer to PHY port '4', and resumes a packet transfer to PHY port '1'.
Figure 7-16 Transmit Multiple Packet Transfer to Different PHY ports (direct status mode)
TCLK TADR TDXA[1] TDXA[2] TDXA[3] TDXA[4] TEN TDATA TSOX TEOP TERR Transfer To Port
'1' 1 2 3 4 '2' 5 6 7 8 9 '3' 10 11 12 13 14 '4' 15 16 17 18 '1' 19 20 P34 P35 P1 P2 ... P41 P42 P19 P20 ... P63 P64 P1 P2 ... P49 P50 P36 P37 P38 '1' '2' '3' '4' '1'
Figure 7-17 shows a multidevice receive interface in byte transfer mode multiple packet transfer from different PHY ports/devices. Prior to clock edge 1, a packet data transfer was initiated from PHY port '1', and PHY ports '2', '3', and '4' indicated to the POS device that they have a block of packet data or an end of packet ready for transfer by asserting their RDXA. On clock edge 2, the POS device indicates to PHY port '1' that it cannot accept any more data transfers by removing its address from RADR, and indicates to PHY port '2' that it is ready to accept a block of packet data by placing its address on RADR and leaving REN asserted. On clock edge 3, PHY port '1' stops transferring packet data, and PHY port '2' starts a packet transfer by leaving RVAL asserted, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 4, PHY port '2' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA. On clock edge 8, the POS device deasserts REN to indicate to PHY port '2' that it cannot accept any more data transfers. On clock edge 9, PHY port '2' ends the packet transfer process by deasserting RVAL and tri-stating its RVAL, RDATA, RSOX, REOP, and RERR outputs. And, the POS device indicates to PHY port '3' that it is ready to accept a block of packet data by placing its address on RADR and reasserting REN. On clock edge 10, PHY port '3' continues a packet transfer by asserting RVAL and placing the next byte of packet data on RDATA. On clock edge 14, PHY port '3' places the last byte of the packet on RDATA, and asserts REOP to indicate that this is the last transfer of the packet. On clock edge 15, PHY port '3' deasserts RVAL and REOP ending the packet transfer 41 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver process, as well as, deasserting RDXA to indicate that it does not have another block of packet data or an end of packet ready for transfer. On clock edge 16, the POS device indicates to PHY port '4' that it is ready to accept a block of packet data by placing its address on RADR and leaving REN asserted. On clock edge 17, PHY port '4' starts a packet transfer by leaving RVAL asserted, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 18, PHY port '4' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA.
Figure 7-17 POS-PHY Level 2 Receive Multiple Packet Transfer from Different PHY Ports/Devices (direct status mode)
RCLK RADR RDXA [1] RDXA [2] RDXA [3] RDXA [4] REN RVAL RDATA RSOX REOP RERR Transfer From PHY
'1' 1 2 3 4 '2' 5 6 7 8 9 10 11 '3' 12 13 14 15 16 17 18 '4' 19 20 P34 P35 P1 P2 ... P41 P42 P43 P19 P20 ... P63 P64 X X P1 P2 P3 P4 '1' '2' 1F '3' '4'
Figure 7-18 shows a multidevice transmit interface in packet transfer mode multiple packet transfer to different PHY ports. On clock edge 2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock edge 4, the POS device selects PHY port 'N'. On clock edge 5, the POS device starts a packet transfer to PHY port 'N' by asserting TEN, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 6, the POS device deasserts TSOX as it continues to place additional bytes of the packet on TDATA. And, PHY port 'N' drives its TSPA output high. On clock edge 10, the POS device polls PHY port 'M'. On clock edge 11, the POS device asserts TEOP to indicate the transfer of the last byte of the packet to PHY port 'N' and PHY port 'M' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock edge 12, the POS device deasserts TEN to end the packet transfer process to PHY port 'N' and selects PHY port 'M'. On clock edge 13, the POS device starts a packet transfer to PHY port 'M' by asserting TEN, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. And, PHY port 'N' tristates its TSPA output. On clock edge 14, the POS device deasserts TSOX as it continues to place additional bytes of the packet on TDATA. And, PHY port 'M' drives its TSPA output high.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-18 POS-PHY Level 2 Transmit Multiple Packet Transfer to Different PHY Ports (polled status mode)
TCLK TADR TPXA TSPA TEN TDAT TSOX TEOP TERR
Transfer To PHY N M X X X X P1 P2 P3 1F M N 1F N N 1F N O 1F O
...
1F L
M
1F M
M
1F M
N
1F N
O
1F O
P
1F P
L
...
P62
P63
P64
X
P1
P2
P3
P4
P5
P6
P7
P8
1
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Figure 7-19 shows a multidevice receive interface in packet transfer mode multiple packet transfer. On clock edge 2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS device that it has a block of packet data or an end of packet ready for transfer by asserting RPXA. On clock edge 4, the POS device selects PHY port 'N'. On clock edge 5, the POS device indicates to PHY port 'N' that it is ready to accept a block of packet data by placing its address on RADR and asserting REN. On clock edge 6, PHY port 'N' starts packet transfer by asserting RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 7, PHY port 'N' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA. On clock edge 14, PHY port 'N' places the last byte of the packet on RDATA, and asserts REOP to indicate that this is the last transfer of the packet. On clock edge 15, PHY port 'N' deasserts RVAL and REOP ending the packet transfer process. On clock edge 16, the POS device deasserts REN and selects PHY port 'P'. On clock edge 17, PHY port 'N' tri-states its RVAL, RDATA, RSOX, REOP, and RERR outputs and the POS device indicates to PHY port 'P' that it is ready to accept a block of packet data by placing its address on RADR and asserting REN. On clock edge 18, PHY port 'P' starts packet transfer by asserting RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 19, PHY port 'P' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA. While this example shows a different PHY port ('P') being selected for the next packet transfer, the timing is identical if the same PHY port ('N') is chosen for the next packet transfer.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-19 POS-PHY Level 2 Receive Multiple Packet Transfer (polled status mode)
RCLK RADR RPXA REN RVAL RDAT RSOX REOP RERR
Transfer From PHY P1 P2 P3 P4 1F M N 1F N N 1F N O 1F O P 1F P
...
1F L
M
1F M
O
1F O
P
1F P
L
1F L
M
...
P61
P62
P63
P64
X
X
P1
P2
P3
N
P
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
7.3.4
POS-PHY Level 3 Functional Timing
Figure 7-20 shows a multiport transmit interface multiple packet transfer to different PHY ports. On clock edge 1, PHY port 'N' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock edge 3, the POS device selects PHY port 'N' by placing its address on TDATA and asserting TSX while TEN is deasserted. On clock edge 4, the POS device starts a packet transfer to PHY port 'N' by deasserting TSX, asserting TEN, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 5, the POS device deasserts TSOX as it continues to place additional bytes of the packet on TDATA and PHY port 'N' asserts TSPA. On clock edge 11, the POS device polls PHY port 'L'. On clock edge 12, PHY port 'N' indicates that it cannot accept any more data transfers by deasserting TSPA. On clock edge 13, PHY port 'L' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock edge 14, the POS device deasserts TEN to end the packet transfer process to PHY port 'N' and selects PHY port 'L' by placing its address on TDATA and asserting TSX while TEN is deasserted. On clock edge 15, the POS device starts a packet transfer to PHY port 'L' by asserting TEN, deasserting TSX, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 16, the POS device deasserts TSOX as it continues to place additional bytes of the packet on TDATA and PHY port 'L' asserts TSPA.
Figure 7-20 POS-PHY Level 3 Transmit Multiple Packet Transfer In-Band Addressing
TCLK TADR TPXA TSPA TEN TSX TDAT TSOX TEOP TERR
Transfer To PHY N L X X N P1 P2 P N L O M P N L O M
... ...
M P
N L
O M
P N
L O
M P
N L
O M
P N
L O
M P
N L
O M
P N
...
P38
P39
P40
P41
P42
P43
P44
L
P1
P2
P3
P4
P5
P6
1
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Figure 7-21 shows a multiport receive-interface multiple packet transfer from different ports. On clock edge 1, the POS device indicates to PHY port 'N' that it is ready to accept a block of packet data by asserting REN. On clock edge 3, the PHY device selects port 'N' for transfer by asserting RSX and placing its address on RDATA. On clock edge 4, PHY port 'N' starts packet transfer by deasserting RSX, asserting RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 5, PHY port 'N' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA. On clock edge 10, PHY port 'N' places the last byte of the packet on RDATA, and asserts REOP to indicate that this is the last transfer of the packet. On clock edge 11, the PHY device deasserts RVAL and REOP ending the packet transfer process from port 'N' and selects PHY port 'L' for transfer by asserting RSX and placing its address on RDATA. On clock edge 12, PHY port 'L' starts packet transfer by deasserting RSX, asserting RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 13, PHY port 'L' deasserts RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 7-21 POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing
RCLK REN RVAL RSX RDAT RSOX REOP RERR
Transfer From PHY N L X N P1 P2 P3
...
P62
P63
P64
L
P1
P2
P3
P4
P5
P6
P7
P8
P9
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8 FUNCTIONAL DESCRIPTION
8.1 Cell / Packet Interface Description
The CELL / PACKET INTERFACE demaps the ATM cells or HDLC packets from a physical data stream in the receive direction and maps ATM cells or HDLC packets into a physical data stream in the transmit direction. In cell mode, the system interface is connected to an ATM Layer device and cells are transported via a UTOPIA 2, UTOPIA 3, POS-PHY 2, or a POS-PHY 3 Bus. In packet mode, the system interface is connected to a Link Layer device and the packets are transported via a POS-PHY 2 or a POS-PHY 3 Bus. The receive direction extracts the payload from physical data stream, performs cell/packet processing on the individual lines, stores the cell/packet data from each line in the FIFO, removes cell/packet data for each port from the FIFO, and outputs the cell/packet data to the ATM/Link Layer device via the system interface. The transmit direction inputs the cell/packet data from the ATM/Link Layer device via the system interface, stores the cell/packet data for each port in the FIFO, removes the cell/packet data for each line from the FIFO, performs cell/packet processing for each individual lines, multiplexes the individual lines into the payload, and inserts the payload into the physical data stream. The Receive Channel Mark and Transmit Channel Mark registers in the receive and transmit framer section are used to map channels (DS0s) to the cell/packet interface.
8.1.1
Reset Descriptions
Unless noted otherwise, during a reset (RESET pin low) all inputs will be ignored, and all outputs will be low. Unless noted otherwise, during a data path reset (LDRST bit = 0), with the exception of the register interface signals, all inputs will be ignored, and all should be low. During a data path reset, the register interface signals will operate normally allowing the registers to be written and read.
8.1.2
BIT / BYTE Ordering
The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB last. The bits in a byte in an incoming signal are numbered in the order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in memory, the MSB is stored in the highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a byte in memory and the corresponding byte in a signal.
8.2
8.2.1
UTOPIA/POS-PHY/SPI-3 System Interface
General Description
The UTOPIA/POS-PHY system interface transports ATM cells or HDLC packets between the DS26556 and an ATM or Link Layer device. In UTOPIA mode, the DS26556 is connected to an ATM layer device and cells are transported via a UTOPIA L2 or UTOPIA L3 Bus. In POS-PHY packet mode, the DS26556 is connected to a Link Layer device and the packets are transported via a POS-PHY 2 or a POS-PHY 3 (or SPI-3) Bus. In POS-PHY cell mode, the DS26556 is connected to an ATM layer device and cells are transported via a POS-PHY 2 or a POSPHY 3 (or SPI-3) Bus. The system interface supports 8-bit or 16-bit transfers at a rate of 52 MHz or less. The receive direction removes cell/packet data for each port from the FIFO, and outputs the cell/packet data to the ATM/Link Layer device via the system interface. The transmit direction inputs the cell/packet data from the ATM/Link Layer device via the system interface, and stores the cell/packet data for each port in the FIFO.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8.2.2
*
Features
* * * *
Programmable system interface type - When performing cell mapping/demapping, the system interface can be programmed as a UTOPIA Level 2 Bus, a UTOPIA Level 3 Bus, a POS-PHY Level 2 Bus, or a POS-PHY Level 3 (or SPI-3) Bus. When performing packet mapping/demapping, the system interface can be programmed as a POS-PHY Level 2 Bus or a POS-PHY Level 3 (or SPI-3) Bus. Selectable system interface bus width - The data bus can be a 16-bit or 8-bit bus at operations speeds up to 52 MHz. Supports multiple ports on the system interface - Each T1 or E1 line has its own port address for access via the system interface. Supports per-port system loopback - Each port can be placed in system loopback which causes cells/packets from the transmit FIFO to be looped back to the receive FIFO. System interface byte reordering - In 16-bit modes, the received/transmitted order of the bytes transferred across the system interface is programmable. i.e., the first byte received/transmitted by ATM cell / packet processing can be transferred in [15:8] or [7:0].
8.2.6
System Interface Bus Controller
The Transmit and Receive System Interface Bus Controller can be programmed to operate as a UTOPIA Level 2, UTOPIA Level 3, POS-PHY Level 2, or POS-PHY Level 3 (or SPI-3) bus controller. It controls the system interface bus timing and provides a common interface to the Transmit and Receive FIFO for FIFO status polling and cell/packet data transfer. Normally, the first byte transmitted is transferred across the system interface as the most significant byte (TDATA[15:8] in 16-bit mode). If byte reordering is enabled, the first byte transmitted is transferred across the system interface as the least significant byte (TDATA[7:0]).On the receive side, the first byte received is transferred across the system interface as the most significant byte (RDATA[15:8] in 16-bit mode). If byte reordering is enabled, the first byte received is transferred across the system interface as the least significant byte (RDATA[7:0]). See Figure 8-1 and Figure 8-2. Byte reordering is ignored in 8-bit mode.
Figure 8-1 Normal Packet Format in 16-Bit Mode
Bit 15 Byte 1 Byte 3 * * * Byte 2n-3 Byte 2n-1 Bit 0 Byte 2 Byte 4 * * * Byte 2n-2 Byte 2n (n-1)th Transfer nth Transfer 1 Transfer 2
nd st
Transfer
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 8-2 Byte Reordered Packet Format in 16-Bit Mode
Bit 15 Byte 2 Byte 4 * * * Byte 2n-2 Byte 2n Bit 0 Byte 1 Byte 3 * * * Byte 2n-3 Byte 2n-1 (n-1)th Transfer nth Transfer 1 Transfer 2
nd st
Transfer
8.2.6.4
UTOPIA Level 2, Transmit Side
In UTOPIA Level 2, an ATM layer device pushes cells across the system interface. The ATM layer device polls the individual ports of the DS26556 to determine which ports have space available for a cell, and selects a port for cell transfer. More than one PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte is transferred with the cells is programmable. The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[4:0]), transmit enable (TEN), and a transmit data bus consisting of transmit data (TDATA[15:0]), transmit parity (TPRTY), and transmit start of cell (TSOX). It outputs transmit direct cell available (TDXA) and transmit polled cell available (TPXA) signals. The transmit data bus is used to transfer cell data whenever one of the ports is selected for cell data transfer. TSOX is asserted during the first transfer of a cell, cell data is transferred on TDATA, and the data bus parity is indicated on TPRTY. All signals are sampled or updated using TSCLK. The TDXA and TPXA signals are used to indicate when the Transmit FIFO has space available for a programmable number of cells. There is a TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has more space available than a programmable number of cells. TDXA goes low when the associated port's Transmit FIFO is full (does not have space for another cell). TPXA reflects the current status of a port's TDXA signal when the port is polled. The TPXA signal is tri-stated unless one of the ports is being polled for FIFO fill status.
8.2.6.5 UTOPIA Level 3, Transmit Side
In UTOPIA Level 3, the ATM layer device pushes cells across the system interface. The ATM layer device polls the individual ports of the DS26556 to determine which ports have space available for a cell, and selects a port for cell transfer. Only one PHY layer device can be present on a UTOPIA Level 3 bus. Whether or not the HEC byte is transferred with the cells is programmable. The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[7:0]), transmit enable (TEN), and a transmit data bus consisting of transmit data (TDATA[15:0]), transmit parity (TPRTY), and transmit start of cell (TSOX). It outputs transmit direct cell available (TDXA) and transmit polled cell available (TPXA) signals. The transmit data bus is used to transfer cell data whenever one of the ports is selected for cell data transfer. TSOX is asserted during the first transfer of a cell, cell data is transferred on TDATA, and the data bus parity is indicated on TPRTY. All signals are sampled or updated using TSCLK. The TDXA and TPXA signals are used to indicate when the Transmit FIFO has space available for a programmable number of cells. There is a TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has more space available than a programmable number of cells. TDXA goes low when the associated port's Transmit FIFO is full (does not have space for another cell). TPXA reflects the current status of a port's TDXA signal when the port is polled. The TPXA signal is always driven.
8.2.6.6 UTOPIA Level 2, Receive Side
In UTOPIA Level 2, the ATM layer device pulls cells across the system interface. The ATM layer device polls the individual ports to determine which ports have cells available, and selects a port for cell transfer. More than one PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte is transferred with the cells is programmable.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[15:0]), receive parity (RPRTY), and receive start of cell (RSOX), as well as, receive direct cell available (RDXA) and receive polled cell available (RPXA) signals. The receive bus is used to transfer cell data whenever one of the ports is selected for cell data transfer. RSOX is asserted during the first transfer of a cell, cell data is transferred on RDATA, and the data bus parity is indicated on RPRTY. All signals are sampled or updated using RSCLK. The data bus is tri-stated unless REN is asserted (low) and one of the ports is selected for data transfer. The RDXA and RPXA signals are used to indicate when the Receive FIFO has a programmable number of cells available for transfer. There is an RDXA for each port in the device. RDXA goes high when the associated port's Receive FIFO contains more than a programmable number of cells. RDXA goes low when the associated port's Receive FIFO is empty (does not contain any cells). RPXA reflects the current status of a port's RDXA signal when the port is polled. The RPXA signal is tri-stated unless one of the ports is being polled for FIFO fill status.
8.2.6.2 UTOPIA Level 3, Receive Side
In UTOPIA Level 3, the ATM layer device pulls cells across the system interface. The ATM layer device polls the individual ports to determine which ports have cells available, and selects a port for cell transfer. Only one PHY layer device can be present on a UTOPIA Level 3 bus. Whether or not the HEC byte is transferred with the cells is programmable. The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[7:0]), and receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[15:0]), receive parity (RPRTY), and receive start of cell (RSOX), as well as, receive direct cell available (RDXA) and receive polled cell available (RPXA) signals. The receive data bus is used to transfer cell data whenever one of the ports is selected for cell data transfer. RSOX is asserted during the first transfer of a cell, cell data is transferred on RDATA, and the data bus parity is indicated on RPRTY. All signals are sampled or updated using RSCLK. The data bus is always driven. The RDXA and RPXA signals are used to indicate when the Receive FIFO has a programmable number of cells available for transfer. There is an RDXA for each port in the device. RDXA goes high when the associated port's Receive FIFO contains more than a programmable number of cells. RDXA goes low when the associated port's Receive FIFO is empty (does not contain any cell ends). RPXA reflects the current status of a port's RDXA signal when the port is polled. The RPXA signal is always driven.
8.2.6.3 POS-PHY Level 2, Transmit Side
In POS-PHY Level 2, the Link layer device pushes packets across the system interface. The Link layer device polls the individual ports of the DS26556 to determine which ports have space available for packet data, and selects a port for packet data transfer. More than one PHY layer device can be present on a POS-PHY Level 2 bus. The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[4:0]), transmit enable (TEN), and a transmit data bus consisting of transmit data (TDATA[15:0]), transmit parity (TPRTY), transmit start of packet (TSOX), transmit end of packet (TEOP), transmit error (TERR), and transmit modulus (TMOD). It outputs transmit direct packet available (TDXA), transmit polled packet available (TPXA), and transmit selected packet available (TSPA) signals. The transmit data bus is used to transfer packet data whenever one of the ports is selected for packet data transfer. TSOX is asserted during the first transfer of a packet, TEOP is asserted during the last transfer of a packet, TERR is asserted when a packet has an error, TMOD indicates the number of bytes transferred on TDATA during the last transfer of a packet, packet data is transferred on TDATA, and the data bus parity is indicated on TPRTY. All signals are sampled and updated using TSCLK. The TDXA, TPXA, and TSPA signals are used to indicate when the Transmit FIFO has space available for a programmable number of bytes. There is a TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has space available for more than a programmable number of bytes. TDXA goes low when the associated port's Transmit FIFO is full. TPXA reflects the current status of a port's TDXA signal when the system interface is in polled mode. TSPA reflects the current status of a port's TDXA signal when the port is selected. The TSPA signal is tri-stated unless TEN is asserted (low) and one of the ports is selected for packet data transfer. The TPXA signal is tri-stated unless one of the ports is being polled for FIFO fill status.
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8.2.6.4 POS-PHY Level 3 (or SPI-3), Transmit Side
In POS-PHY Level 3 (or SPI-3), the Link layer device pushes packets across the system interface. The Link layer device polls the individual ports of the DS26556 to determine which ports have space available for packet data, and selects a port for packet data transfer. Only one PHY layer device can be present on a POS-PHY Level 3 (or SPI-3) bus. The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit enable (TEN), and a transmit data bus consisting of transmit data (TDATA[15:0]), transmit parity (TPRTY), transmit start of packet (TSOX), transmit end of packet (TEOP), transmit error (TERR), transmit start of transfer (TSX), and transmit modulus (TMOD). It outputs transmit direct packet available (TDXA), transmit polled packet available (TPXA), and transmit selected packet available (TSPA) signals. The transmit bus is used to transfer packet data whenever one of the ports is selected for packet data transfer. TSOX is asserted during the first transfer of a packet, TEOP is asserted during the last transfer of a packet, TERR is asserted when a packet has an error, TMOD indicates the number of bytes transferred on TDATA during the last transfer of a packet, TSX is asserted when the selected FIFO's port address has been placed on TDATA, packet data is transferred on TDATA, and the data bus parity is indicated on TPRTY. All signals are sampled and updated using TSCLK. The TDXA, TPXA, and TSPA signals are used to indicate when the Transmit FIFO has space available for a programmable number of bytes. There is a TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has space available for more than a programmable number of bytes. TDXA goes low when the associated port's Transmit FIFO is full. TPXA reflects the current status of a port's TDXA signal when the port is polled. TSPA reflects the current status of a port's TDXA signal when the port is selected. The TPXA and TSPA signals are always driven.
8.2.6.5 POS-PHY Level 2, Receive Side
In POS-PHY Level 2, the Link layer device pulls packets across the system interface. The Link layer device polls the individual ports to determine which ports have packet data available, and selects a port for packet data transfer. More than one PHY layer device can be present on a POS-PHY Level 2 bus. The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[15:0]), receive parity (RPRTY), receive start of packet (RSOX), receive end of packet (REOP), receive error (RERR), receive data valid (RVAL), and receive modulus (RMOD), as well as, a receive direct packet available (RDXA) signal and a receive polled packet available (RPXA) signal. The receive data bus is used to transfer packet data whenever one of the ports is selected for packet data transfer. RSOX is asserted during the first transfer of a packet, REOP is asserted during the last transfer of a packet, RERR is asserted when a packet has an error, RMOD indicates the number of bytes transferred on RDATA during the last transfer of a packet, RVAL is asserted when the receive data bus is valid, RDATA transfers packet data, and RPRTY indicates the data bus parity. All signals are sampled and updated using RSCLK. The RDXA and RPXA signals are used to indicate when the Receive FIFO has a programmable number of bytes or an end of packet available for transfer. There is an RDXA for each port in the device. RDXA goes high when the associated port's Receive FIFO contains more than a programmable number of bytes or an end of packet. RDXA goes low when the associated port's Receive FIFO is empty. RPXA reflects the current status of a port's RDXA signal when the port is polled. The data bus is tri-stated unless REN is asserted (low) and one of the ports is selected for packet data transfer. The RPXA signal is tri-stated unless one of the ports is being polled for FIFO fill status.
8.2.6.6 POS-PHY Level 3 (or SPI-3), Receive Side
In POS-PHY Level 3, the DS26556 pushes packets across the system interface. The DS26556 selects a port for packet data transfer when it has packet data available. Only one PHY layer device can be present on a POS-PHY Level 3 (or SPI-3) bus. The Receive System Interface Bus Controller accepts a receive clock (RSCLK) and receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[15:0]), receive parity (RPRTY), receive start of packet (RSOX), receive end of packet (REOP), receive error (RERR), receive data valid (RVAL), receive start of transfer (RSX), and receive modulus (RMOD). The receive data bus is used to transfer packet data whenever one of the ports has packet data available for transfer. RSOX is asserted during the first transfer of a packet, REOP is asserted during the last transfer of a packet, RERR is asserted when a packet has an error, RMOD indicates the number of bytes transferred on RDATA during the last transfer of a packet, RSX is asserted when the Link layer port address has been placed on RDATA, RVAL is asserted when the receive data bus is valid, RDATA transfers packet data, and RPRTY indicates the data bus parity. All signals are sampled and updated using RSCLK. The data bus is always driven. 51 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver In POS-PHY Level 3 (or SPI-3) the Receive System Interface Bus Controller determines which port to transfer data from using a round-robin arbitration scheme (the ports are checked one after another in numerical order according to their line number x. A transfer is initiated from a port when it is not almost empty (contains more data than the almost empty level or contains an end of packet). Transfer from a port is terminated when the maximum burst length has been transferred, the FIFO is emptied, or an end of packet is transferred while the Receive FIFO is almost empty (contains the same or less data than the almost empty level and does not contain an end of packet). When a transfer is terminated, a transfer is initiated from the next available port that is not almost empty. At the end of a packet or between a transfer from one port and the transfer from the next port, RVAL will go low for a programmable number of clock cycles (0-7) to allow the POS-PHY master to halt data transfer. At the end of a packet, data transfer will continue from the same port if the port is not almost empty. When the maximum burst length has been transferred, data transfer will continue from the same port if no other port has data available, and the port is not almost empty. The maximum burst length is programmable (8 - 256 bytes in four byte increments), or can be disabled.
8.3
8.3.1
ATM Cell / HDLC Packet Processing
General Description
The ATM cell / packet processing demaps the ATM cells or HDLC packets from the receive data stream and maps ATM cells or HDLC packets into the transmit data stream. ATM cell / packet processing supports any framed or unframed bit synchronous or byte synchronous (octet aligned) data stream. The receive direction extracts the payload from physical data stream, performs cell/packet processing on the individual lines, and stores the cell/packet data from each line in the FIFO. The transmit direction removes the cell/packet data for each line from the FIFO, performs cell/packet processing for each individual line and inserts the payload into the physical data stream. Refer to for the location of the Cell/Packet processing block in the DS26556 devices.
8.3.2
* *
Features
General
Supports bit or byte wide, framed or unframed data lines - Each port is programmable as bit synchronous or octet aligned, the data stream can be framed or unframed, and the clock can be continuous or gapped. Bit reordering - The received/transmitted order of the bits as transferred across the system interface is programmable on a per-port basis. That is, in bit synchronous mode, the first bit received/transmitted by ATM cell/packet processing can be transferred in bit position 7 (15 or 7) or bit position 0 (8 or 0). In octet aligned mode, the bit received/transmitted by ATM cell/packet processing in bit position 7 can be transferred in bit position 7 (15 or 7) or bit position 0 (8 or 0).
ATM Cell Processor
* Programmable HEC insertion and extraction - The transmit side can be programmed to accept cells from the system interface that do or do not contain a HEC byte. If cells are transferred without a HEC byte, the HEC byte will be computed and inserted. If cells are transferred with a HEC byte, then the transferred HEC byte can be programmed to be passed through or overwritten with a newly calculated HEC. The receive side can be programmed to send cells to the system interface that do or don't contain the HEC byte. Programmable erred cell insertion - An HEC error mask can be programmed for insertion of single or multiple errors individually or continuously at a programmable rate. Programmable transmit cell synchronization - The transmit data line can be provisioned to be bit synchronous or octet aligned. Programmable header cell pass-through - Receive cell filtering can pass-through only those cells that matching a programmable header value. Selectable idle/unassigned/invalid/programmable header cell padding and filtering - Transmit cell padding can be programmed for idle cell or programmable header cell padding. The padded cell payload byte contents are also programmable. Receive cell filtering can be programmed for any combination of idle cell, unassigned cell, invalid cell, or programmable header cell filtering. Or, all cell filtering can be disabled. Optional header error correction - Receive side single bit header error correction can enabled.
* * * *
*
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* * * * Separate corrected and uncorrected erred cell counts - Separate counts of erred cells containing a corrected HEC error, and cells containing non-corrected HEC errors are kept. Optional HEC uncorrected erred cell filtering - Uncorrected erred cell extraction can be disabled. Selectable cell scrambling/descrambling - Cell scrambling and/or descrambling can be disabled. The 43 scrambling can be a self-synchronous scrambler (x + 1) over the payload only, a self-synchronous scrambler 31 28 over the entire cell, or a Distributed Sample Scrambler (x + x + 1). Optional HEC calculation coset polynomial addition - The performance of coset polynomial addition during HEC calculation can be disabled.
HDLC Packet Processor
* Programmable FCS insertion and extraction - The transmit side can be programmed to accept packets from the system interface that do or don't contain FCS bytes. If packets are transferred without FCS bytes, the FCS will be computed and appended to the packet. If packets are transferred with FCS bytes, then the FCS can be programmed to be passed through or overwritten with a newly calculated FCS. The receive side can be programmed to send packets to the system interface that do or don't contain FCS bytes. Programmable transmit packet synchronization - The transmit data line can be provisioned to be bit synchronous or octet aligned. Programmable FCS type - The FCS can be programmed to be a 16-bit FCS or a 32-bit FCS. Supports FCS error insertion - FCS error insertion can be programmed for insertion of errors individually or continuously at a programmable rate. Supports bit or byte stuffing/destuffing - The bit or byte synchronous (octet aligned) mode determines the bit or byte stuffing/destuffing. Programmable packet size limits - The receive side can be programmed to abort packets over a programmable maximum size or under a programmable minimum size. The maximum packet size allowed is 65,535 bytes. Selectable packet scrambling/descrambling - Packet scrambling and/or descrambling can be disabled. Separate FCS erred packet and aborted packet counts - Separate counts of aborted packets, size violation packets, and FCS erred packets are kept. Optional erred packet filtering - Erred packet extraction can be disabled Programmable inter-frame fill - The transmit inter-frame fill value is programmable.
* * * * * * * * *
8.3.3
Transmit Cell/Packet Processor
The Transmit Cell Processor and Transmit Packet Processor both receive the 32-bit parallel data stream from the Transmit FIFO, however, only one of the processors will be enabled. Which processor is enabled is determined by the system interface mode. In UTOPIA mode, the Transmit Cell Processor is enabled. In POS-PHY mode, if the CPC1.PMCPE bit is low, the Transmit Packet Processor is enabled. If the CPC1.PMCPE bit (is high, the Transmit Cell Processor is enabled.
8.3.4
Receive Cell/Packet Processor
The Receive Cell Processor and Receive Packet Processor both receive the incoming data stream from the Receive Framer (minus all overhead and stuff data), however, only one of the processors will be enabled. The other will be disabled. Which processor is enabled is determined by the system interface mode. In UTOPIA mode, the Receive Cell Processor is enabled. In POS-PHY mode, if the CPC1.PMCPE bit is low, the Receive Packet Processor is enabled. If the CPC1.PMCPE bit is high, the Receive Cell Processor is enabled. The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB last. The bits in a byte in an incoming signal are numbered in the order they are received , 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the highest numbered bit (7], and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a byte in a register and the corresponding byte in a signal.
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8.3.5
8.3.5.1
Cell Processor
Transmit Cell Processor
The Transmit Cell Processor accepts data from the Transmit FIFO and performs bit reordering, cell padding, HEC processing, cell error insertion, and cell scrambling. The data output from the Transmit Cell Processor can be either a serial data stream (bit synchronous mode) or an 8-bit parallel data stream (octet-aligned mode). Cell processing can be disabled. Disabling cell processing disables cell padding, HEC processing, and cell error insertion. Only bit reordering and cell scrambling are not disabled. When cell processing is disabled, data is continually read out of the Transmit FIFO. When the Transmit FIFO is empty, the output data stream is padded with FFh until the Transmit FIFO contains more data than the "almost empty" level. The 32-bit data words read from the Transmit FIFO are multiplexed into an 8-bit parallel data stream and passed on to bit reordering. Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB is in DT[7] of the outgoing data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit transmitted. If cell processing is disabled the data stream is passed on to cell scrambling, bypassing cell padding, HEC processing, and cell error insertion. Cell padding inserts fill cells. After a cell end, fill cells are inserted into the data stream if the Transmit FIFO does not contain a complete cell. The fill cell type and fill cell payload value are programmable. The resulting data stream is passed on to HEC processing. If cell processing is disabled, cell padding will not be performed. HEC processing calculates a HEC and inserts it into the cell. HEC calculation is a CRC-8 calculation over the four 8 2 6 4 2 header bytes. The polynomial used is x + x + x + 1. The coset polynomial, x + x + x + 1, is added (modulo 2) to the residue. The calculated HEC is then inserted into the byte immediately following the header. HEC coset polynomial addition is programmable. If the cell received from the Transmit FIFO contains a HEC byte, the received HEC byte can be passed through or overwritten with the calculated HEC byte. HEC byte pass through is programmable. If the cell received from the Transmit FIFO does not contain a HEC byte, the calculated HEC byte is inserted into the cell. If cell processing is disabled, HEC processing will not be performed. Cell error insertion inserts errors into the HEC byte. The HEC bits to be errored are programmable. Error insertion can be controlled by a register or by the manual error insertion input (TMEI). The error insertion initiation type (register or input) is programmable. If a register controls error insertion, the number and frequency of the errors are programmable. If cell processing is disabled, cell error insertion will not be performed. Cell scrambling can scramble the 48-byte cell payload, scramble the entire cell data stream, or scramble the data stream with a Distributed Sample Scrambler (DSS). If the payload or the entire data stream is scrambled, a self43 synchronous scrambler with a generation polynomial of x + 1 is used. For payload scrambling, the scrambler scrambles the 48-byte payload, and does not scramble the four header or the HEC bytes. For a DSS scrambled 31 28 data stream, a distributed sample scrambler with a generation polynomial of x + x + 1 is used for scrambling. The transmit DSS scrambler scrambles the 48-byte payload and the four byte header. It scrambles the first HEC bit (HEC[1]) with the first transmit DSS scrambler sample (the transmit DSS scrambler bit from 211 bits earlier), scrambles the second HEC bit (HEC[2]) with the second transmit DSS scrambler sample (the current transmit DSS scrambler bit), and does not scramble the remaining HEC bits (HEC[3:8]). DSS scrambling can only be performed in bit synchronous mode. Cell scrambling is programmable (payload, entire data stream, or DSS). If cell processing is disabled, the entire data stream will be scrambled whenever scrambling is enabled Once all cell processing has been completed, in bit synchronous mode, the 8-bit parallel data stream is multiplexed into a serial data stream and passed on. In octet aligned mode, the 8-bit parallel data stream is passed on.
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8.3.5.2 Receive Cell Processor
The Receive Cell Processor performs cell descrambling, cell delineation, cell filtering, header pattern comparison, OCD detection, HEC error monitoring, HEC byte filtering, and bit reordering. The data coming in can be either a serial data stream (bit synchronous mode) or an 8-bit parallel data stream (octet aligned mode). The type of data stream received affects cell descrambling and cell delineation, however, it does not affect OCD detection, HEC error monitoring, cell filtering, header pattern comparison, HEC byte filtering, or bit reordering. Cell processing can be disabled (clear-channel enable). Disabling cell processing disables cell delineation, OCD detection, cell filtering, header pattern comparison, HEC error monitoring, and HEC byte filtering. Only cell descrambling and bit reordering are not disabled. Cell descrambling can descramble the 48-byte cell payload, descramble the entire cell data stream, or descramble a data stream scrambled by a Distributed Sample Scrambler (DSS). If the payload or the entire data stream is 43 descrambled, a self-synchronous scrambler with a generation polynomial of x + 1 is used for descrambling. Payload descrambling descrambles the 48-byte payload, and does not descramble the four header bytes or the 31 HEC byte. For a DSS scrambled data stream, a distributed sample scrambler with a generation polynomial of x + 28 x + 1 is used for descrambling. The receive DSS scrambler is synchronized to the transmit DSS scrambler by DSS scrambler synchronization. DSS descrambling can only be performed in bit synchronous mode. Cell descrambling is programmable (payload, entire data stream, or DSS). In bit synchronous mode, descrambling is performed one bit at a time, and the serial data stream is demultiplexed in to an 8-bit data stream before being passed on. In octet aligned mode, descrambling is performed 8-bits at a time, and only payload or entire data stream descrambling can be performed. When cell processing is disabled, the entire data stream will be descrambled if descrambling is enabled. DSS Scrambler Synchronization synchronizes the receive DSS scrambler with the transmit DSS scrambler used to scramble the incoming data stream. The DSS Scrambler Synchronization state machine has three states: "Acquisition", "Verification", and "Steady State". The "Acquisition" state adds the transmit DSS scrambler samples from 16 incoming cells into the receive DSS scrambler (32 samples total). The samples are derived from the two MSBs (HEC[1:2]) of the incoming HEC byte. Each time the samples in a cell are loaded into the receive DSS scrambler, the confidence counter is incremented. When the confidence counter reaches 16, DSS scrambler synchronization transitions to the "Verification" state. The "Verification" state verifies the samples in the incoming cells by comparing the samples from the cell with the corresponding receive DSS scrambler bits. Each time both samples from a cell match the corresponding receive DSS scrambler bits, the confidence counter is incremented. Each time one of the samples from a cell does not match the corresponding receive DSS scrambler bit, the confidence counter is decremented if the confidence counter reaches 24, DSS scrambler synchronization transitions to the "Steady State" state. If the confidence counter reaches 8, DSS scrambler synchronization transitions to the "Acquisition" state. The "Steady State" state continues to verify the samples in the incoming cells. Each time both samples from a cell match the corresponding receive DSS scrambler bits, the confidence counter is incremented (maximum count = 24). Each time one of the samples from a cell does not match the corresponding receive DSS scrambler bit, the confidence counter is decremented. If the confidence counter reaches 16, DSS scrambler synchronization transitions to the "Acquisition" state. The DSS scrambler synchronization state diagram is shown in Figure 8-4. DSS scrambler synchronization starts in the "Acquisition" state. Note: All ATM cells are discarded during the "Acquisition" and "Verification" states.
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Figure 8-4 Receive DSS Scrambler Synchronization State Diagram
Steady State
8C
eri fic ati on
F ells ion cat rifi Ve ail
8C ell sP
ass V
8 Cells Fail Verification
Verification
32 Samples Loaded
Acquisition
If cell processing is disabled, a cell boundary is arbitrarily chosen, and the data is divided into "cells" whose size is programmable. If HEC transfer is enabled in the receive system interface, the incoming data stream will be divided into 53-byte "cells". If HEC transfer is disabled in the receive system interface, the data is divided into 52-byte "cells". These cells are then passed on to bit reordering bypassing cell delineation, OCD detection, cell filtering, header pattern comparison, HEC error monitoring, and HEC byte filtering. Cell delineation determines the cell boundary by identifying the header bytes and the HEC byte of a cell, and detects an out of cell delineation (OCD) condition or a change of cell delineation (COCD). Cell delineation is performed offline, and the data path cell boundary is only updated by cell delineation if an OCD condition is present. Performing cell delineation off-line results in fewer cells being discarded when the cell boundary changes. If DSS scrambling is enabled (bit synchronous mode only), only the six least significant bits (LSBs) of the HEC (HEC[3:8]) are used for cell delineation, as the two most significant bits (MSBs) are scrambled. An OCD condition is declared if seven consecutive cells are received with incorrect HEC bytes. An OCD condition is terminated if "Delta" consecutive cells are received with correct HEC bytes, if cell delineation updates the data path cell boundary. All ATM cells are discarded during an OCD condition. A COCD is declared when Cell Delineation updates the data path cell boundary with a cell boundary that is different from the current data path cell boundary . Cell delineation has three states: "Hunt", "Presync", and "Sync". The "Hunt" state searches for the cell boundary. Each time slot is checked for an HEC byte (six LSBs of the HEC byte if DSS is enabled). The cell boundary is set once the header and HEC bytes are identified, and cell delineation transitions to the "Presync" state. The "Presync" state verifies the cell boundary identified in the "Hunt" state. The HEC is checked in each incoming cell. If "Delta" cells (including the "Hunt" to "Presync" transition cell) with a correct HEC are received, cell delineation transitions to the "Sync" state. If a cell with an incorrect HEC is received, cell delineation transitions to the "Hunt" state. The "Sync" state checks the HEC in each cell. If a cell with a correct HEC is received, cell delineation updates the data path cell boundary if an OCD condition is present. If a cell with an incorrect HEC is received, cell delineation transitions to the "Hunt" state. The cell delineation state diagram is shown in Figure 8-5. The cell delineation process starts in the "Hunt" state. In octet-aligned mode, the HEC check is performed one byte at a time, so up to 53 checks may be needed to find the cell boundary. In bit synchronous mode, the HEC check is performed one bit at a time, so up to 424 checks may be needed to find the cell boundary. HEC calculation coset polynomial addition can be disabled. The cell delineation process can be programmed to ignore the first header byte (for DQDB applications) when calculating the HEC. If cell processing is disabled, cell delineation will not be performed. A "Delta" of eight is used for unframed modes and a "Delta" of six is used for framed modes. In bit synchronous 56 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver mode, the serial data stream is demultiplexed into an 8-bit parallel data stream (as determined by the data path cell boundary updated) before being passed on to cell filtering.
Figure 8-5 Cell Delineation State Diagram
Sync
EC s
o Inc
orr ect H
ct H rre EC
De lta C
Incorrect HEC
Presync
Correct HEC
Hunt
Cell filtering discards specific cell types. The 8-bit parallel data stream is monitored for idle, unassigned, and invalid cells. (Cells discarded during cell delineation or DSS descrambling are not monitored for cell filtering.) If cell filtering is enabled and the indicated cell type is found, the cell is discarded. Idle cell, unassigned cell, and invalid cell filtering are programmable. Idle cells have a header value of 00000000 00000000 00000000 00000001. Unassigned cells have a header value of xxxx0000 00000000 00000000 0000xxx0. Where x can be any value. Invalid cells have a header value of xxxxyyyy yyyy0000 00000000 0000xxxx. Where x can be any value and yyyyyyyy can be any value other than 00000000. All cells discarded are counted. If cell processing is disabled, cell filtering will not be performed. Header pattern comparison checks for a specific pattern in the header, and either discards and counts cells with a matching header (discard match), discards and counts cells without a matching header (discard no match), counts cells with a matching header (count match), or counts cells without a matching header (count no match). (Cells discarded during OCD detection, DSS descrambling, or cell filtering processes are not monitored for header pattern comparison.) The 8-bit parallel data stream is monitored for cells that have a header that matches the comparison header. In discard match mode, cells with a matching header are counted and discarded. In discard no match mode, cells without a matching header are counted and discarded. In count match mode, cells with a matching header are counted and passed on. In count no match mode, cells without a matching header are counted and passed on. The comparison header and comparison header pattern mode are programmable. If cell processing is disabled, header pattern comparison will not be performed. HEC error monitoring checks the HEC and detects errored and correctable cell headers. (Cells discarded during OCD detection, DSS descrambling, cell filtering, or header pattern comparisons are not monitored for HEC errors.). HEC Error Monitoring has two states, the "Correction" and "Detection" states. . In the "Correction" state, cells received without any header errors (good cells) are passed on. Cells received with a single header error (correctable cells) are corrected and passed on. The corrected cell count is incremented. Cells received with multiple errors are considered errored cells. If errored cell extraction is enabled, errored cells are discarded, and the errored cell count is incremented. If errored cell extraction is disabled, errored cells are passed on. If a cell is 57 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver received with an incorrect HEC, HEC error monitoring transitions to the "Detection" state. In the "Detection" state, good cells are passed on. Cells received with one or more errors are considered errored cells. If m cells are received with a correct HEC or the data path cell boundary is updated, HEC error monitoring will transition to the "Correction" state. The value of m is programmable (1, 2, 4, or 8). The HEC Error Monitoring state diagram is shown in Figure 8-6. HEC Error Monitoring starts in the "Correction" state. If header error correction is disabled, HEC error monitoring will remain in the "Detection" state. If cell processing is disabled, HEC error monitoring will not be performed.
Figure 8-6 HEC Error Monitoring State Diagram
corrected cell
m th good cell
C orrection
cell boundary update errored cell
D etection
HEC byte filtering discards the HEC byte. If HEC transfer is disabled in the receive system interface, the HEC byte is extracted from the cell and discarded. The resulting 52-byte cell is then passed on for storage in the Receive FIFO. If HEC transfer is enabled, the 53-byte cell is passed on for storage in the Receive FIFO. If cell processing is disabled, HEC byte filtering will not be performed. Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB is in DT[7] of the outgoing FIFO data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit received. Once all cell processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel data stream and passed on to the Receive FIFO. Cells are stored in the Receive FIFO in a cell format. regardless of whether or not they are transferred across a UTOPIA or POS-PHY interface.
Figure 8-7 Cell Format for 53-Byte Cell With 16-Bit Data Bus
Bit 15 Header 1 Header 3 HEC Payload 1 * * * Payload 45 Payload 47 Bit 0 Header 2 Header 4 00h Payload 2 * * * Payload 46 Payload 48 26 Transfer 27 Transfer
th th
1 Transfer 2
nd rd th
st
Transfer
3 Transfer 4 Transfer
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 8-8 Cell Format for 52-Byte Cell With 16-Bit Data Bus
Bit 15 Header 1 Header 3 Payload 1 * * * Payload 45 Payload 47 Bit 0 Header 2 Header 4 Payload 2 * * * Payload 46 Payload 48 25 Transfer 26 Transfer
th th
1 Transfer 2
nd rd
st
Transfer
3 Transfer
8.3.6
8.3.6.1
Packet Processor
Transmit Packet Processor
The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The data output from the Transmit Packet Processor can be either a serial data stream (bit synchronous mode) or an 8bit parallel data stream (octet-aligned mode). The type of data stream output from the Transmit Packet Processor affects stuffing, abort insertion, inter-octet padding, inter-frame padding, and packet scrambling, however, it does not affect bit reordering, FCS processing, or packet error insertion. Packet processing can be disabled. Disabling packet processing disables FCS processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame padding. Only bit reordering and packet scrambling are not disabled. When packet processing is disabled, data is continually read out of the Transmit FIFO. When the Transmit FIFO is read empty, the output data stream will be padded with FFh until the Transmit FIFO contains more data than the "almost empty" level. The 32-bit data words read from the Transmit FIFO are multiplexed into an 8-bit parallel data stream and passed on to bit reordering. Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB is in DT[7] of the outgoing data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit transmitted. If packet processing is disabled the data stream is passed on to packet scrambling, bypassing FCS processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame padding. If packet processing is disabled in bit synchronous mode, the serial data stream is demultiplexed in to an 8-bit data stream before being passed on. FCS processing calculates a FCS and appends it to the packet. FCS calculation is a CRC-16 or CRC-32 calculation 16 12 5 32 over the entire packet. The polynomial used for FCS-16 is x + x + x + 1. The polynomial used for FCS-32 is x 26 23 22 16 12 11 10 8 7 5 4 2 + x + x + x + x + x + x + x + x + x + x + x + x + x + 1. The FCS is inverted after calculation. The FCS type is programmable. If FCS append is enabled, the calculated FCS is appended to the packet. If FCS append is disabled, the packet is transmitted without a FCS. The FCS append mode is programmable. If packet processing is disabled, FCS processing is not performed. Packet error insertion inserts errors into the FCS bytes. A single FCS bit is corrupted in each errored packet. The FCS bit corrupted is changed from errored packet to errored packet. Error insertion can be controlled by a register or by the manual error insertion input (TMEI). The error insertion initiation type (register or input) is programmable. If a register controls error insertion, the number and frequency of the errors are programmable. If FCS append is disabled, packet error insertion will not be performed. If packet processing is disabled, packet error insertion is not performed. Stuffing inserts control data into the packet to prevent packet data from mimicking flags. Stuffing is performed from the beginning of a packet until the end of a packet. In bit synchronous mode, the 8-bit parallel data stream is multiplexed into a serial data stream, and bit stuffing is performed. Bit stuffing consists of inserting a '0' directly following any five contiguous '1's. In octet aligned mode, byte stuffing is performed. Byte stuffing consists of detecting bytes that mimic flag and escape sequence bytes (7Eh and 7Dh), and replacing the mimic bytes with an escape sequence (7Dh) followed by the mimic byte exclusive ORed with 20h. If packet processing is disabled, stuffing is not performed. 59 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Inter-frame padding inserts start flags, end flags and inter-frame fill between packets. There will be at least one flag plus a programmable number of additional flags between packets. In octet aligned mode, the inter-frame fill is flags. In bit synchronous mode, the inter-frame fill can be flags or all 1s followed by a start flag. If the inter-frame fill is all '1's, the number of '1's between the end and start flags may not be an integer number of bytes, however, there will be at least 15 consecutive '1's between the end and start flags. The bit synchronous mode inter-frame padding type is programmable. If packet processing is disabled, inter-frame padding is not performed. Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. In bit synchronous mode, the abort sequence is FFh. In octet aligned mode, the abort sequence is 7D7Eh. If packet processing is disabled, packet abort insertion is not performed. The packet scrambler is a x + 1 self-synchronous scrambler that scrambles the entire packet data stream. Packet scrambling is programmable. Once all packet processing has been completed, in bit synchronous mode, the 8-bit parallel data stream is multiplexed into a serial data stream and passed on. In octet aligned mode, the 8-bit parallel data stream is passed on.
8.3.6.2 Receive Packet Processor
43
The Receive Packet Processor performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The data coming in can be either a serial data stream or an 8-bit parallel data stream, depending on the framing mode The type of data stream received affects packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, and destuffing, however, it does not affect packet size checking, FCS error monitoring, FCS byte extraction, or bit reordering. Packet processing can be disabled (clear-channel enable). Disabling packet processing disables packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, and FCS byte extraction. Only packet descrambling and bit reordering are not disabled. The packet descrambler is a self-synchronous x + 1 descrambler that descrambles the entire packet data stream. Packet descrambling is programmable. If packet processing is disabled in bit synchronous mode, the serial data stream is demultiplexed in to an 8-bit data stream before being passed on. If packet processing is disabled, a packet boundary is arbitrarily chosen, and the data is divided into "packets" whose size is programmable (maximum packet size setting). These packets are then passed on to bit reordering bypassing packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, and FCS byte extraction. Packet delineation determines the packet boundary by identifying a packet start or end flag. Each time slot is checked for a flag sequence (7Eh). Once a flag is found, it is identified as a start or end flag, and the packet boundary is set. If packet processing is disabled, packet delineation is not performed. Inter-frame fill filtering removes the inter-frame fill between packets. When a packet end flag is detected, all data is discarded until a packet start flag is detected. In bit synchronous mode, the inter-frame fill can be flags or all '1's. When the interframe fill is all `1's, the number of '1's between the start and end flags does not need to be an integer number of bytes. In bit synchronous mode when inter-frame fill is flags, there may be only one flag between packets, or the flags may have a shared zero (011111101111110). In octet aligned mode, the inter-frame fill can only be flags, and there may be only one flag between packets. If packet processing is disabled, inter-frame fill filtering is not performed. Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is incremented, and all subsequent data is discarded until a packet start flag is detected. In bit synchronous mode, the abort sequence is seven consecutive ones. In octet aligned mode, the abort sequence is 7D7Eh. If packet processing is disabled, packet abort detection is not performed. Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. In bit synchronous mode, bit destuffing is performed. Bit destuffing consists of discarding any '0' that directly follows five contiguous '1's. In octet aligned mode, byte destuffing is performed. Byte destuffing consists of detecting an escape sequence (7Dh), discarding it and exclusive ORing the next byte with 20h. In bit synchronous mode, after destuffing is completed, the serial bit stream is demultiplexed into an 8-bit parallel data stream and passed on to packet size checking. If there is less than eight bits in the last byte, an invalid packet flag is raised, the packet is tagged with an abort indication, and the packet size violation count is incremented. In octet aligned mode, after destuffing is 60 of 362
43
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver completed, the 8-bit parallel data stream is passed on to packet size checking. If packet processing is disabled, destuffing is not performed. Packet size checking checks each packet for a programmable maximum and programmable minimum size. As the packet data comes in, the total number of bytes is counted. If the packet length is below the minimum size limit, the packet is marked with an aborted indication, and the packet size violation count is incremented. If the packet length is above the maximum size limit, the packet is marked with an aborted indication, the packet size violation count is incremented, and all packet data is discarded until a packet start is received. The minimum and maximum lengths include the FCS bytes, and are determined after destuffing has occurred. If packet processing is disabled, packet size checking is not performed. FCS error monitoring checks the FCS and aborts errored packets. If a FCS error is detected, the FCS errored packet count is incremented and the packet is marked with an aborted indication. The FCS type (16-bit or 32-bit) is programmable. If FCS processing or packet processing is disabled, FCS byte extraction is not performed. FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet. If FCS processing or packet processing is disabled, FCS byte extraction is not performed. Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB is in DT[7] of the outgoing FIFO data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit received. Once all packet processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel data stream and passed on to the Receive FIFO.
8.3.7
8.3.7.1
FIFO
Transmit FIFO
The Transmit FIFO block contains memory for 64 32-bit data words. The Transmit FIFO separates the transmit system interface timing from the transmit physical interface timing. The Transmit FIFO functions include filling the memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions. The number of data transfers that can occur after the Transmit FIFO "full" indication is deasserted is programmable. The Transmit FIFO port address used for selection and polling by the Transmit System Interface Bus Controller is programmable. In system loopback, the data from the Transmit FIFO is looped back to the Receive FIFO, and a FIFO empty indication is passed on to the Transmit Cell/Packet Processor. In cell processing mode, all operations are cell based. The Transmit FIFO is considered empty when it does not contain any data. The Transmit FIFO is considered "almost empty" when it does not contain a cell. The Transmit FIFO is considered "almost full" when it does not have space available to store a programmable number of cells. The Transmit FIFO is considered full when it does not have space available for a complete cell. When the Transmit FIFO level drops below the "almost full" indication, the TDXA[n] is asserted. The Transmit FIFO accepts cell transfers from the Transmit System Interface Bus Controller until it is full. If a start of cell is received while full, the cell is discarded and a FIFO overflow condition is declared. Once a FIFO overflow condition is declared, the Transmit FIFO will discard cell data until a start of cell is received while the FIFO has more space available than the "almost full" level. If the Transmit FIFO receives cell data other than a start of cell after a complete cell has been received, an invalid transfer is declared and all cell data is discarded until a start of cell is received. If a start of cell is received before a previous cell transfer has been completed, the current cell is discarded and a short transfer is declared. The new cell is processed normally. If the Transmit Cell Processor attempts a read while the Transmit FIFO is empty, a FIFO underflow condition is declared. Once a FIFO underflow condition is declared, the Transmit FIFO data will be discarded until a start of cell is received. In packet processing mode, all operations are byte based. The Transmit FIFO is considered empty when its memory does not contain any data. The Transmit FIFO is considered "almost empty" when its memory does not contain a packet end and there is a programmable number of bytes or less stored in the memory. The Transmit FIFO is considered "almost full" when its memory has a programmable number of bytes or less available for storage. When the Transmit FIFO has more bytes available for storage than the "almost full" level the TDXA[n] or TPXA pin will be asserted to signal to the POS device that it is ready to receive more packet data. The Transmit FIFO is considered full when it does not have any space available for storage. When the Transmit FIFO is full, the TDXA[n] pin will be deasserted. The Transmit FIFO accepts data from the Transmit System Interface Bus Controller until full. If a start of packet or short packet (32-bit data word with a start of packet and end of packet) is received while full, the data is discarded and a FIFO overflow condition is declared. If any other packet data is 61 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver received while full, the current packet being transferred is marked with an abort indication, and a FIFO overflow condition is declared. Once a FIFO overflow condition is declared, the Transmit FIFO will discard data until a start of packet is received while the FIFO has more space available than the "almost full" level. If a packet error (a transfer with TERR and TEOP asserted) is received from the Transmit System Interface Bus Controller, an aborted transfer is declared, the data is stored in memory with a packet abort indication, and the Transmit FIFO will discard data until a start of packet is received. If an end of a packet has been received and the Transmit FIFO receives packet data other than a start of packet, an invalid transfer is declared, and all packet data is discarded until a start of packet is received. If a start of packet is received before a previous packet transfer has been completed (an end of packet was never received), the current packet being transferred is marked with an abort indication and a short transfer is declared. The new packet is processed normally. If the Transmit Packet Processor attempts a read while the Transmit FIFO is empty, a FIFO underflow condition is declared. Once a FIFO underflow condition is declared, the Transmit FIFO data will be discarded until a start of cell is received.
8.3.7.2 Receive FIFO
The Receive FIFO block contains memory for 64 32-bit data words. The Receive FIFO separates the receive system interface timing from the receive physical interface timing. The Receive FIFO functions include filling the memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions. The Receive FIFO port address used for selection and polling by the Receive System Interface Bus Controller is programmable. In system loopback, data is looped back from the Transmit FIFO to the Receive FIFO. In cell processing mode, all operations are cell based. The Receive FIFO is considered empty unless it contains a cell. The Receive FIFO is considered "almost empty" when it contains a programmable number of cells or less. When the Receive FIFO level has more data available for transfer than the "almost empty" level, the RDXA[n] pin is asserted. The Receive FIFO is considered "almost full" when it does not have space available to store a complete cell. The Receive FIFO is considered full when it does not have any space available. The Receive FIFO accepts cell data from the Receive Cell Processor until full. If cell data is received while the FIFO is full, the cell is discarded and a FIFO overflow condition is declared. Once a FIFO overflow condition is declared, the Receive FIFO will discard cell data until a cell start is received while the FIFO has space available to store a complete cell. If the Receive System Interface Bus Controller attempts a read while the FIFO is empty, the read is ignored. In packet processing mode, all operations are 32-bit word based. The Receive FIFO is considered empty when it does not contain any data. The Receive FIFO is considered "almost empty" when its memory does not contain a packet end and there is a programmable number of words or less stored in the memory. When the Receive FIFO has more bytes available for transfer than the "almost empty" level or has an end of packet, the RDXA[n] pin is asserted (POS-PHY Level 2). The Receive FIFO is considered "almost full" when its memory has a programmable number of words or less available for storage. The Receive FIFO is considered full when it does not have any space available for storage. The Receive FIFO accepts data from the Receive Packet Processor until full. If a packet start or short packet is received while full, the data is discarded and a FIFO overflow condition is declared. If any other packet data (packet end or middle) is received while full, the current packet being received is marked with an abort indication, and a memory overflow condition is declared. Once a memory overflow condition is declared, the Receive FIFO will discard data until a packet start is received while the FIFO has more space available than the "almost full" level. If the Receive System Interface Bus Controller attempts a read while the FIFO is empty, the read is ignored.
8.3.8
System Loopback
There is a system loopback available in the ATM/HDLC Mapper. The loopback can be performed on a per-port basis. When a port is placed in system loopback, the data coming in from the System Interface is looped back from the Transmit FIFO to the Receive FIFO, a FIFO empty indication is passed on to the Transmit Cell/Packet Processor, and all data coming from the Receive Cell/Packet Processor is discarded. The maximum throughput of a single port is limited to half of the Receive System Interface bandwidth in 16-bit mode. A loss of data may occur if the Cell Packet Receive clock (RSCLK) has a frequency that is greater than one and one half times the Cell Packet Transmit clock (TSCLK).
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8.4
T1 Receive Framer Description and Operation
The DS26556 includes four fully independent DS1/E1 framers. Each framer can be individually programmed to accept AMI, B8ZS, HDB3, or NRZ data. In T1 mode, each framer supports D4 (SF), ESF, and SLC-96 frame formats, and detects/reports common alarms such as AIS, RAI, LOS, and OOF, as well as AIS-CI and RAI-CI. Performance monitor counters are maintained for each port, which report bipolar/line-code violations, F-bit/CRC errors, and number of out-of-sync multiframes. Each framer has an HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode), and has 64-byte FIFO buffers in both the transmit and receive paths. The HDLC controllers perform the necessary overhead for generating and receiving performance report messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controllers automatically generate and detect flags; generate and check the CRC checksum; generate and detect abort sequences and stuff and destuff zeros; and byte align to the data stream. The FIFO buffers are large enough to allow a full PRM to be received or transmitted without host intervention. Other features contained within each framer include a BOC detector with programmable code integration and three independent 16-bit loop-code detectors. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported in both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin.
8.4.1
T1 Loopbacks
Figure 8-9 Remote Loopback
RECEIVE FRAMER
BACKPLANE I/F
TRANSMIT FRAMER
BACKPLANE I/F
REMOTE LOOPBACK
In this loopback, data input at the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues to pass through the DS26556's receive-side framer as it would normally, and the data from the transmitside formatter is ignored.
Figure 8-10 Payload Loopback
RECEIVE FRAMER
BACKPLANE I/F
TRANSMIT FRAMER
BACKPLANE I/F
PAYLOAD LOOPBACK (CAN BE DONE ON A PER-CHANNEL BASIS) 63 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver When PLB is enabled, the following occurs: 1) Data is transmitted from the TTIP and TRING pins synchronous with RCLK instead of TCLK. 2) All the receive-side signals continue to operate normally. 3) TCHMKR is forced low. 4) Data at the TDATAI pin is ignored. Normally, this loopback is only enabled when ESF framing is being performed, but it can also be enabled in D4 framing applications. In a PLB situation, the DS26556 loops the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS26556.
Figure 8-11 Framer Loopback
RECEIVE FRAMER
BACKPLANE I/F
TRANSMIT FRAMER
BACKPLANE I/F
FRAMER LOOPBACK
This loopback is useful in testing and debugging applications. In FLB, the DS26556 loops data from the transmit side back to the receive side. When FLB is enabled, the following occurs: 1) (T1 mode) An unframed all-ones code is transmitted at TTIP and TRING. (E1 mode) Normal data is transmitted at TTIP and TRING. 2) Data at RTIP and RRING is ignored. 3) All receive-side signals take on timing synchronous with TCLK instead of RCLK.
8.4.2
H.100 (CT Bus) Compatibility
The H.100 (or CT Bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit, H100EN (RIOCR.5), when combined with HSSYNCINV, allows the DS26556 to accept a CT-Bus-compatible frame-sync signal (CT_FRAME) at the HSSYNC input. The following rules apply to the H100EN control bit: 1) The H100EN bit controls the sampling point for the HSSYNC input signal only. 2) The H100EN bit does not invert the expected signal; HSSYNCINV (TIOCR) must be set high to invert the inbound sync signal.
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Figure 8-12 HSSYNC Input in H.100 (CT Bus) Mode
HSSYNC 1
HSSYNC 2
HSYSCLK HTDATA, HRDATA
Bit 8 Bit 1 Bit 2
tbc3
NOTE 1: HSSYNC IN NORMAL OPERATION. NOTE 2: HSSYNC WITH H100EN = 1 and HSSYNCINV = 1. NOTE 3: tbc (BIT-CELL TIME) = 122ns (typ). tbc = 244ns or 488ns ALSO ACCEPTABLE.
8.4.3
T1 Receive Status and Information
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. Status bits can operate in either a latched or real-time fashion. Some latched bits can be enabled to generate a hardware interrupt through the INT signal.
Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the internal status signals can be read at any time from the real-time status registers without changing any of the latched status register bits. Latched Bits When an event or an alarm occurs and a latched bit is set to 1, it remains set until the user clears it. These bits typically respond on a change-of-state for an alarm, condition, or event, and operate in a read-then-write fashion. The user should read the value of the desired status bit and then write a 1 to that particular bit location to clear the latched value (write a zero to locations not to be cleared). Once the bit is cleared, it is not set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin through the interrupt mask registers (RIMx). When unmasked, the INT signal is forced low when the enabled event or condition occurs. The INT pin is allowed to return high (if no other unmasked interrupts are present) when the user reads, then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin clear even if the alarm is still present.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Note that some conditions can have multiple status indications. For example, receive loss-of-frame (RLOF) provides the following indications: Real-time indication that the receiver is not synchronized with incoming data stream. Read-only bit that remains high as long as the condition is present. Latched indication that the receiver has lost synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (rising edge detect of RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (falling edge detect of RRTS1.0).
RRTS1.0 (RLOF)
RLS1.0 (RLOFD)
RLS1.4 (RLOFC)
Table 8-1 T1 Alarm Criteria
ALARM AIS (Blue Alarm) (Note 1) RAI (Yellow Alarm) 1) D4 Bit 2 Mode (RCR2.0 = 0) SET CRITERIA CLEAR CRITERIA
When over a 3ms window, 5 or fewer zeros are received When bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences When the 12th framing bit is set to one for two consecutive occurrences
When over a 3ms window, 6 or more zeros are received When bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences When the 12th framing bit is set to zero for two consecutive occurrences
2) D4 12th F-Bit Mode (RCR2.0 = 1; also referred to as the Japanese Yellow Alarm)
3) ESF Mode
When 16 consecutive patterns of 00FF appear in the FDL When 192 consecutive zeros are received
When 14 or less patterns of 00FF hex out of 16 possible appear in the FDL When 14 or more ones out of 112 possible bit positions are received starting with the first one received
LOS (also referred to as Receive Carrier Loss (RCL))
Note 1: The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate properly in the presence of a 10E-3 error rate, and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria in the DS26556 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit. Note 2: The following terms are equivalent: RAIS = Blue Alarm RLOS = RCL RLOF = Loss of Frame RRAI = Yellow Alarm
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8.4.4
Receive AIS-CI and RAI-CI Detection
AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all ones pattern and 0.15 seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones (T1.403). AIS-CI is an unframed pattern and therefore is defined for all T1 framing formats. The RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1.2) is set. RAIS-CI is a latched bit and should be cleared by the host when read. RAIS-CI will continue to set approximately every 1.2 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal AIS indicators to determine when the condition has cleared. RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of "00000000 11111111" (right-to-left) with 90ms of "00111110 11111111". The RRAI-CI bit is set when a bit-oriented code of "00111110 11111111" is detected while RRAI (RRTS1.3) is set. The RRAI-CI detector uses the receive BOC filter bits (RBF0 & RBF1) located in RBOCC to determine the integration time for RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read. RRAI-CI will continue to set approximately every 1.1 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to enable the 200ms ESF RAI integration time with the RAIIE control bit (RCR2.1) in networks that use RAI-CI.
8.4.5
T1 Receive-Side Digital Milliwatt Code Generation
Receive-side digital milliwatt code generation involves using the receive-digital milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registers, represents a particular channel. If a bit is set to 1, then the receive data in that channel is replaced with the digital milliwatt code. If a bit is set to zero, no replacement occurs.
8.4.6
T1 Error Count Registers
The DS26556 contains three T1 performance counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only), or manually. See the Error Counter Configuration Register (ERCNT) section. When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. The line-code violation count register has the potential to saturate, but the bit error would have to exceed 10E-2 before this would occur. All other counters roll over. Several options are available for latching the performance counters: 1) Each framer's counters are latched independently based on independent one-second interval timers. 2) Each framer's counters are latched independently based on independent 42ms interval timers. 3) Each framer's counters are latched independently with a low-to-high transition on the respective MECU control bit. 4) Counters from selected framers are latched synchronously at the one-second interval supplied by Framer #1. 5) Counters from selected framers are synchronously latched manually with the global counter latch-enable (GCLE) bit in GCR1. The following table shows control bit settings in the ERCNT register to support each of the five modes discussed above.
Control Bit EAMS ECUS MECU MCUS 1SECS Mode 1 0 0 0 0 0 Mode 2 0 1 0 0 0 Mode 3 1 X 0 to 1 0 0 Mode 4 0 0 0 0 1 Mode 5 1 0 0 1 0
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8.4.7
T1 Receive Signaling Operation
There are two methods of accessing receive-signaling data: through processor-based (i.e., software-based) signaling or hardware-based signaling. Processor-based refers to access through the receive-signaling registers, RS1 through RS12. Hardware-based refers to the HRSIG pin. Hardware based signaling is available only when the port is configured in the multiplexed bus mode utilizing the high speed TDM port. Both methods can be used simultaneously. NOTE: The receive framer does not normally remove robbed-bit signaling from the data stream. Signaling information is present in the data stream at the RSER pin unless the receive framer has been programmed to over-lay certain channels with idle codes or to force signaling bit positions to a "one" state. The signaling data in data stream at the HRDATA pin can be re-aligned to a users multiframe reference. See Signaling Re-insertion below.
8.4.8
Software Signaling
Robbed-bit signaling (the LSB of each channel during frames 6, 12, 18 and 24 in ESF mode and frames 6 and 12 in D4 mode ) is sampled in the receive data stream and copied into the receive-signaling registers, RS1 through RS12. The signaling information in these registers is always updated on multiframe boundaries. This function is referred to as "Software Based Signaling" and is always enabled. The signaling bit position of each channels is sampled even thought the channel may not be carrying signaling information. The user may simply ignore these channels.
8.4.8.1 Change of State To avoid constant monitoring of the receive-signaling registers, the DS26556 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. For T1, RSCSE1 through RSCSE3 are used to select which channels can cause a change-of-state indication. The change of state is indicated in latched status register 4 (RLS4.3). The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the interrupt mask bit RIM4.3.
The user can identify which channels have undergone a signaling change of state by reading the receive-signaling status (RSS1-RSS3) registers. The information from these registers tells the user which RSx register to read for the new signaling data. All changes are indicated in the RSS1 through RSS3 registers regardless of the state of t he RSCSE1 through RSCSE3 registers.
8.4.9
Hardware Signaling
A TDM signaling stream is available via the HRSIG pin when the port is configured to use the high speed multiplexed TDM bus. HRSIG is a signaling-PCM stream output on a channel-by-channel basis from the signaling buffer and multiplexed with any other port configured to use the high speed TDM bus. In ESF mode the HRSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each channel. The HRSIG data is updated once a multiframe (1.5ms) unless a freeze is in effect.
8.4.9.1 Signaling Debounce When signaling integration is enabled (RSIGC.0 = 1), the signaling data at the HRSIG pin is automatically debounced. Signaling must be constant for three multiframes before being updated at HRSIG. Signaling debounce is enabled on a global basis (all channels or none). NOTE: This feature is available only on the high speed TDM bus.
8.4.10 Signaling Re-insertion
The signaling buffer allows signaling data to be reinserted into the original data stream in a different alignment determined by a multiframe sync signal from the HSSYNC pin. Registers RSI1 through RSI4 are used to select signaling re-insertion on a channel-by-channel basis. Ports configured to be multiplexed on the high speed TDM bus can have the same signaling alignment. In T1 mode re-insertion generally results in there being two copies of robbed signaling for each port in the data stream, one at the original position and one at the user defined position. NOTE: It is possible to configure only one port to the high speed multiplexed bus. In this case the RSER pin for that port and the HRDATA pin are duplicates.
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8.4.11 Receive Signaling Freeze
NOTE: This feature is available only on the high speed TDM bus. The signaling data in the four multiframe signaling buffer will be frozen in a known good state upon either a loss of framing (RLOF), carrier loss (RLOS), or change of frame alignment (COFA). To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2) high. The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the HRSIG pin (and at the HRDATA pin if receive signaling reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data will be held in the last known good state until the error condition subsides. The signaling data will be held in the old state for at least an additional 6ms before being allowed to update with new signaling data.
8.4.12 Fractional T1 Support (Gapped-Clock Mode)
The DS26556 can be programmed to output gapped clocks for selected channels in the receive and transmit paths. When the gapped-clock feature is enabled, a gated clock is output on the RCHMRK pin. The channel selection is controlled through the receive-gapped-clock channel-select registers (RGCCS1-RGCCS4). The receive path is enabled for gapped-clock mode with the RGCE bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
8.4.13 T1 Bit-Oriented Code (BOC) Controller
The DS26556 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. In ESF mode, the DS26556 continuously monitors the receive message bits for a valid BOC message. The BOCdetect (BD) status bit at RLS7.0 is set once a valid message has been detected for time determined by the receiveBOC-filter bits RBF0 and RBF1 in the RBOCC register. The 6-bit BOC message is available in the RBOC register. Once the user has cleared the BD bit, it remains clear until a new BOC is detected (or the same BOC is detected following a BOC-clear event). The BOC-clear (BC) bit at RLS7.1 is set when a valid BOC is no longer being detected for a time determined by the receive-BOC-disintegration bits RBD0 and RBD1 in the RBOCC register. The BD and BC status bits can create a hardware interrupt on the INT signal as enabled by the associated interrupt mask bits in the RIM7 register.
8.4.14 Receive SLC-96 Operation
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. To enable the DS26556 to synchronize onto an SLC-96 pattern, the following configuration should be used:

Set to D4 framing mode (RCR1.5 = 1) Set to cross-couple Ft and Fs bits (RCR1.3 = 1) Enable SLC-96 synchronizer (RCR2.4 = 1) Set to minimum sync time (RCR1.7 = 0)
The status bit RSLC96 located at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit indicates when the framer has received the 12-bit Fs-alignment pattern and updated the data-link registers RSLC1-RSLC3 with the latest message data from the incoming data stream. Once the RSLC96 bit is set, the user has 2ms to retrieve the most recent message data from the RSLC1/2/3 registers. Note that RSLC96 is not set if the DS26556 is unable to detect the 12-bit SLC-96 alignment pattern.
8.4.15 Receive FDL
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register (RFDL). Since the RFDL is 8 bits in length, it fills up every 2ms (8 x 250ms). The framer signals an external microcontroller that the buffer has filled through the RLS7.2 bit. If enabled through RIM7.2, the INT pin toggles low, indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no zero destuffing is applied for the data provided through the RFDL register. 69 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8.4.16 Programmable In-Band Loop-Code Detection
The DS26556 can generate and detect a repeating bit pattern from 1 to 8 bits or 16 bits in length. This function is available only in T1 mode. The framer has three programmable pattern detectors. Typically, two of the detectors are used for loop-up and loop-down code detection. The user programs the codes to be detected in the receive-upcode definition (RUPCD1 and RUPCD2) registers and the receive-down-code definition (RDNCD1 and RDNCD2) registers, and the length of each pattern is selected through the RIBCC register. A third detector (spare) is defined and controlled through the RSPCD1/RSPCD2 and RSCC registers. When detecting a 16-bit pattern, both receivecode-definition registers are used together to form a 16-bit register. For 8-bit patterns, both receive-code-definition registers are filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive-code-definition register to be filled. The framer detects repeating pattern codes in framed and unframed circumstances with bit-error rates as high as 10E-2. The detectors can handle F-bit-inserted and F-bit-overwrite patterns. Writing the least significant byte of the receive-code-definition register resets the integration period for that detector. The code detector has a nominal integration period of 36ms. Therefore, after about 36ms of receiving a valid code, the proper status bit (LUP, LDN, and LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN, and LSP (RRTS3 and RLS3). Normally codes are sent for 5 seconds. It is recommended that the software poll the framer every 50ms to 1000ms until 5 seconds has elapsed to ensure the code is continuously present.
8.4.17 Receive HDLC Controller
The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode). The HDLC controller performs the necessary overhead for generating and receiving performance report messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags; generates and checks the CRC checksum; generates and detects abort sequences and stuffs and destuffs zeros; and byte aligns to the data stream. The 64-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
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8.4.18 Receive HDLC Controller Example
The HDLC status registers in the DS26556 allow for flexible software interface to meet the user's preferences. When receiving HDLC messages, the host can choose to be interrupt-driven, or to poll to desired status registers, or a combination of polling and interrupt processes can be used. shows an example routine for using the DS26556 HDLC receiver.
Figure 8-13 Receive HDLC Example
Configure Receive HDLC Controller (RHC, RHBSE, RHFC)
Reset Receive HDLC Controller (RHC.6)
Start New Message Buffer
Enable Interrupts RPE and RHWM
Interrupt?
NO
No Action Required Work Another Process
YES Read Register RHPBA
Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0]
NO
MS = 0?
(MS = RHPBA[7])
YES
Read RRTS5 for Packet Status (PS2..0) Take appropriate action
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8.5
T1 Transmit Formatter Description and Operation
Four fully independent DS1/E1 transmit formatters are included within the DS26556. Each port can be individually programmed to transmit AMI, B8ZS, HDB3, or NRZ data. In T1 mode each formatter supports D4 (SF), ESF, and SLC-96 frame formats, and transmits common alarms such as AIS, RAI, AIS-CI, and RAI-CI. Each framer also has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode) and has 64 byte FIFO buffers in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controllers, as well as specific Sa bits (E1 Mode). The HDLC controllers perform all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The controllers automatically generate and detects flags, generate and check the CRC check sum, generate and detect abort sequences, stuff and de-stuff zeros, and byte align to the data stream. The large FIFO buffers allow a full PRM to be received or transmitted without host intervention. Other features contained within each framer include a BOC generator and a 16-bit loop code generator. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be enabled to generate an external interrupt on the INT pin. Additional details concerning the operation of the DS1 formatter are included within the register descriptions within this section.
8.5.1
T1 Per-Channel Loopback
The Per-Channel Loopback Registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back.
8.5.2
T1 Transmit DS0 Monitoring Function
The DS26556 has the ability to monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM[4:0] = 00101 RCM[4:0] = 01110
8.5.3
T1 Transmit Signaling Operation
There are two methods of providing transmit signaling data--processor-based (i.e., software-based) or hardwarebased. Processor-based refers to access through the transmit signaling registers, TS1 through TS12, while hardware-based refers to using the HTSIG pins. Hardware based signaling is available only when the port is configured in the multiplexed bus mode utilizing the high speed TDM port. Both methods can be used simultaneously. Note: Signaling data may already be imbedded in the transmit data streams at the TSER or HTDATA pins. In this case the two methods mentioned above may be used to update any or all channels.
8.5.3.1 Software Signaling Signaling data is loaded into the Transmit Signaling registers (TS1-TS12) via the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the Transmit Multiframe Interrupt in Latched Status
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register. Each Transmit Signaling Register contains the robbed bit signaling for two time slots that will be inserted into the outgoing stream if enabled to do so via TCR1.6. Signaling data can be sourced from the TSx registers on a perchannel basis by utilizing the Software Signaling Insertion Enable registers, SSIE1 through SSIE3. In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1 through TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses A and B bit positions for the next multiframe. The C and D bit positions become `don't care' in D4 mode.
8.5.3.2 Hardware Signaling Hardware signaling is only available when the port is configured to use the high speed TDM bus. Note: the cell/packet interface is unavailable to this port in this mode. In hardware mode, signaling data is input via the HTSIG pin. This signaling PCM stream is demultiplexed, buffered and inserted to the data stream input from the demultiplexed HTDATA pin.
The user has the ability to control which channels are to have signaling data from the HTSIG pin inserted into them on a per-channel basis via the THSCS1 through THSCS3 registers.
8.5.4
T1 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Twenty-four Transmit Idle Definition Registers (TIDR1-TIDR24) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-3) are used to enable idle code replacement on a per channel basis.
8.5.5
T1 Transmit Channel Mark Registers
The Transmit Channel Mark Registers (TCMR1/TCMR2/TCMR3/TCMR4) control the mapping of channels to the transmit cell/packet interface and the TCHMRK pin. The TCHMRK signal is used internally to select which channels will be mapped to the transmit cell/packet interface. Externally, the signal can be used to multiplex TDM data into channels not used by the transmit cell/packet interface. When the appropriate bits are set to 1, the transmit cell/packet function is mapped to that channel and externally the TCHMRK pin is held high during the entire corresponding channel time. In T1 mode, only RCMR1 to RCMR3 and the LSB of RCMR4 are used.
8.5.6
Fractional T1 Support (Gapped Clock Mode)
The DS26556 can be programmed to output gapped clocks for selected channels in transmit path. When the TCHMRK pin is in the channel clock mode and gapped channel clock is enabled, a gated clock is output on the TCHMRK pin during selected channel times. The channel selection is controlled via the transmit-gapped-clock channel-select registers (TGCCS1-TGCCS4). If TCHMRK is in the channel clock mode, clock mode is enabled by the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
8.5.7
T1 Transmit Bit Oriented Code (BOC) Controller
The DS26556 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Bits 0 through 5 in the TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6) causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as SBOC is set. Note that the TFPT (TCR1.6) control bit must be set to 'zero' for the BOC message to overwrite F-bit information being sampled on TSER.
8.5.8
T1 Transmit FDL
When enabled with TCR2.7, the transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data 73 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver stream. After the full eight bits has been shifted out, the framer will signal the host microcontroller that the buffer is empty and that more data is needed by setting the TLS2.4 bit to a one. The INT will also toggle low if enabled via TIM2.4. The user has 2ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. Note that in this mode, no zero stuffing will be applied to the FDL data. In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register must be programmed to 1Ch and the following bits must be programmed as shown: TCR2.7 = 0 (source Fs data from the TFDL register) TCR2.6 = 1 (allow the TFDL register to load on multiframe boundaries).
8.5.9
Transmit SLC-96 Operation
In a SLC-96 based transmission scheme, the standard Fs bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC- 96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12 bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. To insert the SLC-96 message fields, the user has the option to either use the external TLINK pin or the use the onboard TFDL register. Use of the TLINK pin will require additional circuitry, and to enable this option the TCR2.7 bit should be set to one. To insert the SLC-96 message using the TFDL register, the user should configure the DS26556 as shown below: TCR2.6 (TSLC96) = 1 TCR2.7 (TFDLS) = 0 TCR3.2 (TFM) = 1 TCR1.6 (TFPT) = 0 Enable Transmit SLC-96 Source FS bits via TFDL or SLC96 formatter D4 framing Mode Do not 'pass through' TSER F-bits.
The DS26556 will automatically insert the 12-bit alignment pattern in the Fs bits for the SLC96 data link frame. Data from the TSLC1-TSLC3 will be inserted into the remaining Fs bit locations of the SLC96 multiframe. The status bit TSLC96 located at TLS1.4 will set to indicate that the SLC96 data link buffer has been transmitted and that the user should write new message data into TSLC1-TSLC3. The host will have 2.5ms after the assertion of TLS1.4 to write the registers TSLC1-TSLC3. If no new data is provided in these registers, the previous values will be retransmitted.
8.5.10 Transmit HDLC Controller
The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 Mode). The HDLC controller performs all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream.
8.5.10.1 Transmit HDLC FIFO Control Control of the transmit FIFO is accomplished via the Transmit HDLC FIFO Control (THFC). The FIFO Control register sets the watermarks for the receive FIFO.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register will be set. TLWM is a real-time bit and remains set as long as the transmit FIFO's write pointer is below the watermark. If enabled, this condition can also cause an interrupt via the INT pin.
8.5.11 HDLC Transmit Example
The HDLC status registers in the DS26556 allow for flexible software interface to meet the user's preferences. When transmitting HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26556 HDLC transmitter is given in Figure 8-14 HDLC Message Transmit Example.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 8-14 HDLC Message Transmit Example
Configure Transmit HDLC Controller
(THC1,THC2,THBSE,THFC)
Reset Transmit HDLC Controller (THC.5)
Enable TLWM Interrupt and Verify TLWM Clear
Set TEOM (THC1.2)
Read TFBA N = TFBA[6..0]
Push Last Byte into Tx FIFO
Push Message Byte into Tx HDLC FIFO (THF) Loop N Last Byte of Message? NO TLWM Interrupt? YES NO NO YES
Enable TMEND Interrupt
TMEND Interrupt? YES Read TUDR Status Bit
NO
A
A
TUDR = 1
A
No Action Required Work Another Process
Disable TMEND Interrupt Prepare New Message
YES
Disable TMEND Interrupt Resend Message
8.5.12 Programmable In-Band Loop-Code Generator
The DS26556 can generate and detect a repeating bit pattern from one to eight bits or sixteen bits in length. This function is available only in T1 mode. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition registers (TCD1&TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in Transmit Control Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern both transmit code definition registers (TCD1&TCD2) must be filled with the proper code. Generation of a 3, 5, 6 and 7 bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. 75 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver As an example, to transmit the standard "loop-up" code for Channel Service Units (CSUs), which is a repeating pattern of ...10000100001..., set TCD1 = 80h, TC0=0, TC1=0, and TCR3.0 = 1.
8.5.13 Interfacing the T1 Tx Formatter to the BERT
Data from the BERT can be inserted into the DS26556 transmit formatter data stream. Either framed or unframed format can be transmitted, controlled by the TBFUS bit in the TBICR. Any signal DS0, combination of DS0s, or the entire bandwidth can be replaced with the BERT data as controlled by the TBCS registers.
8.5.14 T1 Transmit Synchronizer
When enabled, the DS26556 transmitter has the ability to identify the D4 or ESF frame boundary within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC register. The Transmit Latched Status 3 (TLS3) register provides a latched status bit (LOFD) to indicate that a Loss-of-Frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INT. Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the recovered frame sync pulse will be output on this signal. The recovered multiframe sync pulse will be output if enabled with TIOCR.0 (TSM = 1).
8.6
E1 Receive Framer Description and Operation
Four fully independent DS1/E1 framers are included within the DS26556. Each framer can be individually programmed to accept AMI, HDB3 (E1), B8ZS (T1), or NRZ data. In E1 mode each framer supports FAS, CRC-4, and CAS frame formats, and detects/reports common alarms such as AIS, RAI, LOS, and LOF. Performance monitor counters are maintained for each port that reports bipolar/line code violations, CRC-4 errors, FAS errors, and E-bits. Each framer has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode) and includes 64 byte FIFO buffers in both the transmit and receive paths. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin.
8.6.1
H.100 (CT Bus) Compatibility
The H.100 (or CT Bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with HSSYNCINV allows the DS26556 to accept the CT-Bus compatible frame sync signal (/CT_FRAME) at the HSSYNC input. The following rules apply to the H100EN control bit: 1) The H100EN bit controls the sampling point for the HSSYNC only. 2) The H100EN bit in RIOCR controls HSSYNC. 3) The H100EN bit does not invert the expected signal; HSSYNCINV (TIOCR) must be set `high' to invert the inbound sync signals.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 8-15 HSSYNC Input in H.100 (CT Bus) Mode
HSSYNC 1
HSSYNC 2
HSYSCLK HTDATA, HRDATA
Bit 8 Bit 1 Bit 2
tbc3
NOTE 1: HSSYNC IN NORMAL OPERATION. NOTE 2: HSSYNC WITH H100EN = 1 and HSSYNCINV = 1. NOTE 3: tbc (BIT-CELL TIME) = 122ns (typ). tbc = 244ns or 488ns ALSO ACCEPTABLE.
8.6.2
E1 Error Count Registers
The DS26556 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only), or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at their respective maximum counts and they will not rollover. The Line-Code Violation Count Register has the potential to saturate, but the bit error would have to exceed 10E-2 before this would occur. All other counters will roll over. Several options are available for latching the performance counters: 1) Each framer's counters are latched independently based on independent one-second interval timers. 2) Each framer's counters are latched independently based on independent 62.5ms interval timers. 3) Each framer's counters are latched independently with a low to high transition on the respective MECU control bit. 4) Counters from selected framers are latched synchronously at the one-second interval supplied by framer_#1. 5) Counters from selected framers are synchronously latched manually with the Global Counter Latch Enable (GCLE) bit in GCR1. The following table shows configuration bit settings in the ERCNT register for each of the 5 modes mentioned above:
Control Bit EAMS ECUS MECU MCUS 1SECS Mode 1 0 0 0 0 0 Mode 2 0 1 0 0 0 Mode 3 1 X 0 to 1 0 0 Mode 4 0 0 0 0 1 Mode 5 1 0 0 1 0
8.6.2.1 E1 Line Code Violation Count Register (LCVCR) Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side; HDB3 codewords are not counted as BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined 77 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** - 2 before the VCR would saturate. See Table 8-2.
Table 8-2 E1 Line Code Violation Counting Options
E1 CODE VIOLATION SELECT (ERCNT.0) 0 1 WHAT IS COUNTED IN THE LCVCRs BPVs CVs
8.6.3
DS0 Monitoring Function
The DS26556 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The RCM0 to RCM4 bits should be programmed with the decimal decode of the appropriate E1 channel. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into RDS0SEL: RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
8.6.4
E1 Receive Signaling Operation
Signaling data is sampled in the receive data stream and copied into the receive signaling registers, RS1 through RS16. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. NOTE: The receive framer does not normally remove TS16 signaling from the data stream. Signaling information is present in the data stream at the RSER pin unless the receive framer has been programmed to over-lay TS16 with idle codes or to force signaling bit positions to a "one" state. The signaling data in data stream at the HRDATA pin can be re-aligned to a users multiframe reference. See Signaling Reinsertion below. CAS signaling (time slot 16) is sampled in the receive data stream and copied into the receive-signaling registers, RS1 through RS16. The signaling information in these registers is always updated on CAS multiframe boundaries. This function is referred to as "Software Based Signaling" and is always enabled. Time slot 16 is always sampled and loaded into the signaling registers even though CAS signaling data may not be present. When the high speed multiplexed TDM bus is utilized, a TDM signaling stream is available at the HRSIG pin. This is referred to as "Hardware Based Signaling".
8.6.4.1 Change Of State In order to avoid constantly monitoring of the receive signaling registers the DS26556 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1 through RSCSE4 for E1 are used to select which channels can cause a change of state indication. The change of state is indicated in Latched Status Register 4 (RLS4.3). If signaling integration is enabled then the new signaling state must be constant for 3 multiframes before a change of state indication is indicated. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the appropriate interrupt mask bit RIM4.3. The signaling integration mode is global and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the Receive Signaling Status (RSS1 through RSS4) registers. The information from these registers tells the user which RSx register to read for the new signaling data. All changes are indicated in the RSS1-RSS4 registers regardless of the RSCSE1- RSCSE4 registers. 78 of 362
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8.6.4.2 Hardware-Based Receive Signaling HRSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The ABCD signaling bits are output on HRSIG in the lower nibble of each channel. HRSIG is updated once per CAS multiframe (2ms) unless a freeze is in effect. TS16 signaling data is still present in the original data stream at RSER. A signaling buffer provides signaling data to the HRSIG pin and also allows signaling data to be re-inserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNC pin.
When signaling integration is enabled the signaling data at RSIG is automatically debounced. Signaling must be constant for three multiframes before being up-dated at RSIG. Signaling debounce is enabled on a global basis.
8.6.5
Fractional E1 Support (Gapped Clock Mode)
The DS26556 can be programmed to output gapped clocks for selected channels in receive path. When the RCHMRK pin is in the channel clock mode and gapped channel clock is enabled, a gated clock is output on the RCHMRK pin during selected channel times. The channel selection is controlled via the receive-gapped-clock channel-select registers (RGCCS1-RGCCS4). If RCHMRK is in the channel clock mode, clock mode is enabled by the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
8.6.6
Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode)
When operated in the E1 mode the DS26556 receiver provides extended access to both the Sa and the Si bits. The RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the Receive Align Frame bit in Latched Status Register 2 (RLS2.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the RLS2.0 bit to know when to read the RAF and RNAF registers. The host has 250ms to retrieve the data before it is lost. Also there are eight registers (RsiAF, RSiNAF, RRA, Rsa4 to Rsa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions below for additional information.
8.6.7
HDLC Overhead Control Receive Example
The HDLC status registers in the receive framer allow for flexible software interface to meet the user's preferences. When receiving HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26556 HDLC receiver is given in Figure 8-16.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 8-16 Receive HDLC Example
Configure Receive HDLC Controller (RHC, RHBSE, RHFC)
Reset Receive HDLC Controller (RHC.6)
Start New Message Buffer
Enable Interrupts RPE and RHWM
Interrupt?
NO
No Action Required Work Another Process
YES Read Register RHPBA
Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0]
NO
MS = 0?
(MS = RHPBA[7])
YES
Read RRTS5 for Packet Status (PS2..0) Take appropriate action
8.6.8
Interfacing the E1 Rx Framer to the BERT
The Receive BERT receives data from the framer when the receive BERT is enabled. Any single DS0 or combination of DS0s can be extracted from the data stream up to the entire T1 payload as controlled by the RBCS registers. Details concerning the on-chip BERT can be found in Section 13.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8.6.9
E1 Transmit Formatter Description and Operation
Four fully independent DS1/E1 transmit formatters are included within the DS26556. Each port can be individually programmed to transmit AMI, HDB3 (E1), or NRZ data. In E1 mode, each formatter supports FAS, CRC-4, and CAS frame formats, transmits common alarms such as AIS and RAI. Each transmitter has an HDLC controllers which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode) or the FDL (T1 mode) and has 64-byte FIFO buffers in both the transmit and receive paths. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin. Additional details concerning the operation of the E1 formatter are included within the register descriptions within this section.
8.6.10 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (TCR2.6 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer forces an AIS. When automatic RAI generation is enabled (TCR2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant Remote Alarm will be transmitted if the DS26556 cannot find CRC4 multiframe synchronization within 400ms as per G.706. Note: It is an illegal state to have both automatic AIS generation and automatic Remote Alarm generation enabled at the same time.
8.6.11 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
When a port is operating in a full or partial TDM mode and the E1 CRC framing structure is present in the data stream at TSER, the transmit framer can recalculate the CRC4 check-sum. The recalculation will take into account any changes made to the Sa bits by the host without disturbing any bit error information contained in CRC4 structure present at TSER. The E1 transmit framer can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions and this change in data content will be used to modify the CRC-4 checksum. This modification however will not corrupt any error information the original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode. The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input then the user must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe-align the data presented to TSER. This mode is enabled with the TCR3.0 control bit (CRC4R).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 8-17 CRC Update Flow Diagram
TPOSO/TNEGO
INSERT NEW CRC-4 CODE
EXTRACT OLD CRC-4 CODE
TSER
+
CRC-4 CALCULATOR
XOR
MODIFY Sa BIT POSITIONS
NEW Sa BIT DATA
8.6.12 E1 Transmit DS0 Monitoring Function
The DS26556 can monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SELregister. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
8.6.13 E1 Transmit Signaling Operation
There are two methods of providing transmit signaling data--processor-based (i.e., software-based) or hardwarebased. Processor-based refers to access through the transmit signaling registers, TS1 through TS16, while hardware-based refers to using the HTSIG pins. Hardware based signaling is available only when the port is configured in the multiplexed bus mode utilizing the high speed TDM port. Both methods can be used simultaneously. Note: Signaling data may already be imbedded in the transmit data streams at the TSER or HTDATA pins. In this case the two methods mentioned above may be used to update any or all channels.
8.6.13.1 Software Signaling Signaling data is loaded into the Transmit Signaling registers (TS1-TS16) via the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the Transmit Multiframe Interrupt in Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register.
Each Transmit Signaling Register contains the TS16 CAS signaling (E1) for one time slot that will be inserted into the outgoing stream if enabled to do so via TCR1.6. Signaling data can be sourced from the TS registers on a perchannel basis by utilizing the Software Signaling Insertion Enable registers, SSIE1 through SSIE4. TS16 carries the signaling information. This information can be in either CCS (Common Channel Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel number schemes 82 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver in E1. In "Channel" numbering, TS0 through TS31 are labeled channels 1 through 32. In "Phone Channel" numbering TS1 through TS15 are labeled channel 1 through channel 15 and TS17 through TS31 are labeled channel 15 through channel 30.
8.6.13.2 Hardware Signaling Hardware signaling is only available when the port is configured to use the high speed TDM bus. Note: the cell/packet interface is unavailable to this port in this mode. In hardware mode, signaling data is input via the HTSIG pin. This signaling PCM stream is demultiplexed, buffered and inserted to the data stream input from the demultiplexed HTDATA pin.
The user has the ability to control which channels are to have signaling data from the HTSIG pin inserted into them on a per-channel basis via the THSCS1 through THSCS4 registers.
Figure 8-18 Time Slot Numbering Schemes
TS Channel Phone Channel 0 1 1 2 1 2 3 2 3 4 3 4 5 4 5 6 5 6 7 6 7 8 7 8 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
8.6.14 Fractional E1 Support (Gapped Clock Mode)
The DS26556 can be programmed to output gapped clocks for selected channels in transmit path. When the TCHMRK pin is in the channel clock mode and gapped channel clock is enabled, a gated clock is output on the TCHMRK pin during selected channel times. The channel selection is controlled via the transmit-gapped-clock channel-select registers (TGCCS1-TGCCS4). If TCHMRK is in the channel clock mode clock mode is enabled by the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
8.6.15 Additional (Sa) and International (Si) Bit Operation (E1 Mode)
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Transmit Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update the TAF and TNAF registers. It has 250ms to update the data or else the old data will be retransmitted. NOTE: If the TAF an TNAF registers are only being used to source the align frame and non-align frame sync patterns then the host need only write once to these registers. Data in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. There is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that, via the Transmit Sa-Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted.
8.6.16 E1 Transmit HDLC Controller
Each framer port has an HDLC controller with 64-byte FIFOs. The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 mode). This block has 64-byte FIFO buffers in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode). The HDLC controllers automatically generate and detect flags, generate and check the CRC checksum, generate and detect abort sequences, stuff and destuff zeros, and byte align to the data stream.
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8.6.17 E1 HDLC Transmit Example
The HDLC status registers in the DS26556 allow for flexible software interface to meet the user's preferences. When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used.
Figure 8-19 E1 HDLC Message Transmit Example
Configure Transmit HDLC Controller
(THC1,THC2,THBSE,THFC)
Reset Transmit HDLC Controller (THC.5)
Enable TLWM Interrupt and Verify TLWM Clear
Set TEOM (THC1.2)
Read TFBA N = TFBA[6..0]
Push Last Byte into Tx FIFO
Push Message Byte into Tx HDLC FIFO (THF) Loop N Last Byte of Message? NO TLWM Interrupt? YES NO NO YES
Enable TMEND Interrupt
TMEND Interrupt? YES Read TUDR Status Bit
NO
A
A
TUDR = 1
A
YES No Action Required Work Another Process
Disable TMEND Interrupt Prepare New Message Disable TMEND Interrupt Resend Message
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8.6.18 Interfacing the E1 Transmitter to the BERT
If the Transmit BERT is enabled, data will be inserted from the BERT into the transmit formatter. Any single DS0 or combination of DS0s can be inserted into the data stream up to the entire T1 payload as controlled by the RBCS registers. Details concerning the BERT can be found in Section 13.
8.6.19 E1 Transmit Synchronizer
The DS26556 transmitter can identify the E1 frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. Control signals for the transmit synchronizer are located in the TSYNCC register. The Transmit Synchronizer Status (TSYNCS) register provides a latched status bit (LOFD) to indicate that a loss-of-frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INT. Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the recovered frame sync pulse will be output on this signal. The recovered CRC4 multiframe sync pulse will be output if enabled with TIOCR.0 (TSM = 1).
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9 LINE INTERFACE UNIT (LIU)
The DS26556's LIU provides the necessary transmit pulse shaping and receive signal processing for long-haul, short-haul, FCC CSU build-outs, and clock-synchronization applications. The transmitter and receiver have software selectable, internal termination for 75W, 100W, 110W, and 120W networks. The LIU block also contains a jitter attenuator that can be assigned to either the transmit or receive path, or disabled. Several loopbacks are provided for network and system side diagnostics. Each port's LIU can be configured independently. The table below describes the registers involved in control and configuration of the LIUs.
9.1
9.1.1
LIU Transmitter
Pulse Shapes
The transmit pulse shape is configured on a port-by-port basis. Pulse shapes are typically measured and compared to the appropriate pulse template at two locations in the network. For T1 long haul and FCC CSU applications the pulse is measured at the near-end NI (Network Interface). For T1 short haul applications the pulse is measured at the far-end NI. All E1 pulse shapes are measured at the near-end NI.
9.1.2 Transmit Termination
The LIU Transmit Impedance Selection Registers can be used to select an internal Transmit Terminating Impedance of 100W for T1, 110W for J1 Mode, 75W or 120W for E1 Mode, or no internal Termination for E1 or T1 Mode. In this case the user has to provide the Line Terminating Network. The transmit pulse shape and terminating impedance is selected by the LTCR register.
9.1.3 Power-Down and High-Z
The DS26556 provides the ability to individually power-down the transmitters and/or place the transmit drivers into a High-Z state via register bits or device pins. This is useful for Protection Switching applications. The transmitters can be powered down by setting the TPDE bit in the LCCR2 register. Note that powering down the transmit LIU results in a High-Z state for the corresponding TTIP and TRING pins.
9.1.4 Transmit All Ones
When Transmit All Ones is invoked in the LIU block, continuous ones are transmitted using MCLK as the timing reference. Data and clock from the framer is ignored. Transmit all ones can be sent by setting a bit in the LCCR2 register. Also transmit all ones will be are sent if the corresponding receiver goes into LOS state and the ATOS bit is set in the LCCR2 register.
9.1.5 Driver Fail Monitor
The transmit drivers have a monitor that will detect short circuit and open-circuit conditions at the TTIP and TRING pins. The drive current will be limited if a short circuit is detected. The status registers can be used to alert the user to an open circuit or short circuit condition.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 9-1 T1/J1 Transmit Pulse Templates
1.2 1.1
N O R M AL IZ ED A M PL IT UD E
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template
-0.1 -0.2 -0.3 -0.4 -0.5 -500 -400
-300
-200
-100
0
100 200 TIME (ns)
300
400
500
600
700
DSX-1 Template (per ANSI T1.102 1993) MAXIMUM CURVE MINIMUM CURVE
UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 Time -500 -255 -175 -175 -75 0 175 225 600 750 Amp. 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 UI -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Time -500 -150 -150 -100 0 100 150 150 300 430 600 750 Amp. -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05
DS1 Template (per ANSI T1.403 199 )
MAXIMUM CURVE Time Amp. UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.34 0.77 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.20 1.20 1.05 1.05 -0.05 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.61 0.93 1.16
MINIMUM CURVE UI Time Amp. -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.26 -0.05 -0.05
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 9-2 E1 Transmit Pulse Templates
1.2 1.1 1.0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 Template
TIME (ns)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
9.2
Receiver
The receiver can function with "cable loss" signal attenuation of up to 36 dB for T1 Mode and 43 dB for E1 Mode. The receiver's sensitivity can be limited to 12 dB for E1 mode or 15dB for T1 mode. For bridged monitor applications a resistive gain setting can be enabled to provide 14, 20, 26, and 32 dB of resistive gain. The peak detector and data slicer process the received signal. The output of the data slicer goes to a clock and data recovery circuit. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery system that derives the E1 or T1 clock. The clock recovery system uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding performance to meet jitter tolerance specifications.
9.2.1 Receiver Monitor Mode
Bridged monitor port isolation resistors typically cause resistive losses of 20dB(T1) and 32dB(E1). The receiver front end can be programmed for a fixed gain of 14dB, 20dB, 26dB, and 32dB to compensate for the monitor port's loss. 12dB to 30dB of "cable loss" compensations is still available in monitor applications. See table as shown in LIU Receive Control Register (Section 9.2.1).
Figure 9-3 Typical Monitor Operation
T1/E1 LINE
PRIMARY T1/E1 TERMINATING DEVICE Rm
X F M R
Rm
Rt
DS26556
MONITOR PORT JACK
SECONDARY T1/E1 TERMINATING DEVICE
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
9.2.2
Peak Detector and Slicer
The Slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock and data recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for determination of the slicing threshold.
9.2.3 Clock and Data Recovery
The resultant E1 or T1/J1 clock derived from the 2.048/1.544 PLL (JACLK in) is internally multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in Figure 9-5.
9.2.4 Receive Level Indicator The signal strength at RTIP and RRING is reported in approximate 2.5dB increments via RSL3-RSL0 in the LRSL register. This feature is helpful when trouble-shooting line-performance problems. The DS26556 can initiate an interrupt whenever the input falls below a certain level through the input-level under-threshold indicator (SR1.7). Using the RLT0-RLT4 bits of the CCR4 register, the user can set a threshold in 2.5dB increments. The SR1.7 bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in RLT0-RLT4. The level must remain below the programmed threshold for approximately 50ms for this bit to be set. The accuracy of the receive level indication is 1 LSB (2.5dB) from 25C to 85C and 2 LSB's (5dB) from -40C to 25C. 9.2.5 Loss of Signal
The DS26556 uses both the digital and analog loss detection method in compliance with the latest T1.231 for T1/J1 and ITU G.775 or ETSI 300 233 for E1 mode of operation. LOS is detected if the received signal level falls below a threshold for a certain duration. Alternatively, this can be termed as having received "zeros" for a certain duration. The signal level and timing duration are defined in accordance with the T1.231 or G.775 or ETSI 300 233 specifications. For short haul Mode, the loss detection thresholds are based on cable loss of 12/18 dB for both T1/J1 and E1 Mode. The loss thresholds are selectable based on criteria defined in Table 9-1. For long-haul mode, the LOS Detection threshold is based on cable loss of 30/38 dB for T1/J1 and 30/45 dB for E1 Mode. Note there is no explicit bit called short-haul mode selection. The setting for the receiver sensitivity is through the LIU receive impedance and sensitivity monitor. The loss state is exited when the receiver detects a certain ones density at a higher signal level than the loss detection level. The loss detection signal level and loss reset signal level are defined with hysteresis to prevent the receiver from bouncing between "LOS" and "no LOS" states. The following table outlines the specifications governing the loss function:
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Table 9-1 Loss Criteria T1.231, G.775 and ETSI 300 233 Specifications
T1.231 No pulses are detected for 175 +/- 75 bits. STANDARD ITU G.775 No pulses are detected for duration of 10 to 255 bit periods. The incoming signal has transitions for duration of 10 to 255 bit periods. ETSI 300 233 No pulses are detected for a duration of 2048 bit periods or 1 msec Loss reset criteria is not defined.
Loss Detection Criteria Loss Reset Criteria
Loss is terminated if a duration of 12.5% ones are detected over duration of 175 +/- 75 bits. Loss is not terminated if 8 consecutive zeros are found if B8ZS encoding is used. If B8ZS is not used loss is not terminated if 100 consecutive pulses are zero.
9.2.5.1
ANSI T1.231 for T1 and J1 Modes
For Short-Haul Mode, loss is detected if the received signal level is less than 15/21 dB for a duration of 192 bit periods. LOS is reset if the all of the following criteria are met: 24 or more ones are detected in 192-bit period with a detection threshold of 12/18 dB measured at RTIP and RRING. * During the 192 bits less than 100 consecutive zeros are detected. For Long-Haul Mode, loss is detected if the received signal level is less than 33/39 dB for a duration of 192 bit periods. LOS is reset if the all of the following criteria are met:
* * 9.2.5.2 *
24 or more ones are detected in 192-bit period with a detection threshold of 30/36 dB measured at RTIP and RRING. During the 192 bits less than 100 consecutive zeros are detected.
ITU G.775 for E1 Modes
For Short-Haul Mode, LOS is detected if the received signal level is less than 15/21 dB for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 12/18 dB for a duration of 192 bit periods. For Long-Haul Mode, LOS is detected if the received signal level is less than 33/46 dB for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 30/43.
9.2.5.3 ETSI 200 233 for E1 Modes
For short-haul mode, LOS is detected if the received signal level is less than 15/21 dB for a continuous duration of 2048 (1 msec) bit periods. LOS is reset if the receive signal level is greater than 12/18 dB for a duration of 192 bit periods. For long-haul mode, LOS is detected if the received signal level is less than 33/46 dB for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 30/43 dB for a duration of 192 bit periods.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 9-4 Jitter Tolerance
1k UNIT INTERVALS (UIP-P) DS2655 TOLERANC TR 62411 (DEC. 90) 10 ITU-T G.823 1
100
0.1
1
10
100 1k FREQUENCY (Hz)
10k
100k
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
9.3
Jitter Attenuator
The DS26556's jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS bit in the LIU Common Control Register (LCCR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 9-5. The jitter attenuator can be placed in either the receive path or the transmit path or disabled by appropriately setting the JAPS1 and JAPS0 bits in the LIU Common Control Register (LCCR). In order for the jitter attenuator to operate properly, a 2.048 MHz or multiple thereof or 1.544 MHz clock or multiple thereof must be applied at MCLK. ITU specification G.703 requires an accuracy of +/-50 ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an accuracy of +/- 32 ppm for T1/J1 interfaces. Onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIP-P (buffer depth is 128 bits) or 28 UIP-P (buffer depth is 32 bits), then the DS26556 will set the jitter attenuator limit trip (JALTSLS) bit in the LIU latched status Register (LLSR) when the FIFO is 8 bits from underflow or overflow. The FIFO pointer will be 8 bits or 120 bits. In T1/J1 Mode the Jitter Attenuator corner frequency is 3.75 Hz and in E1 Mode it is 0.6 Hz.
Figure 9-5 Jitter Attenuation
0dB
TBR12 Prohibited Area ITU G.7XX Prohibited Area
JITTER ATTENUATION (dB)
-20dB
Cu e rv A
E1
T1
-40dB
B rve Cu
TR 62411 (Dec. 90) Prohibited Area
-60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K
9.4
LIU Loopbacks
The DS26556 provides three loopbacks in the LIU block: analog loopback (ALB), local loopback (LLB), and remote loopback (RLB). Remote loopback (RLB) and local loopback (LLB) may be enabled simultaneously. Additionally, the framer block provides framer loopback (FLB) discussed in the framer section of the datasheet.
9.4.1
Analog Loopback
TTIP and TRING are looped to RTIP and RRING. Externally, signals at RTIP and RRING are ignored. 93 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
9.4.2
Local Loopback
Data from the transmit backplane interface is looped back to the receive backplane interface. Data form the transmit system backplane will continue to be transmitted as normal.
9.4.3
Remote Loopback
The inputs decoded from the Receive LIU are looped back to the Transmit LIU. The inputs from the Transmit Framer are ignored during a remote loopback.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
10 OVERALL REGISTER MAP
Table 10-1 Overall Register Map
Address Description
0000 - 01FF 0200 - 03FF 0400 - 05FF 0600 - 07FF 0800 - 09FF 0A00 - 0BFF 0C00 - 0DFF 0E00 - 0FFF 1000 - 11FF 1200 - 13FF 1400 - 15FF 1600 - 17FF 1800 - 18FF 1900 - 19FF 1A00 - 1FFF
Port 1 Framer Port 2 Framer Port 3 Framer Port 4 Framer Port 1 LIU Port 2 LIU Port 3 LIU Port 4 LIU Port 1 Cell/Packet Processor Port 2 Cell/Packet Processor Port 3 Cell/Packet Processor Port 4 Cell/Packet Processor Global Registers System Interface Registers Unused
The address offset for each port: Port 1 - No Offset Port 2 - Port 1 Address + 0200 Hex Port 3 - Port 1 Address + 0400 Hex Port 4 - Port 1 Address + 0600 Hex
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Table 10-2 Per Port Register Map
Address offset Description
0000 - 00DF 00E0 - 00EF 00F0 - 00FF 0100 - 01DF 01E0 - 01FF 0800 - 080F 0810 - 09FF 1000 - 103F 1040 - 104F 1050 - 107F 1080 - 108F 1090 - 10FF 1100 - 111F 1120 - 117F 1180 - 118F 1190 - 11FF 1800 - 181F 1820 - 18FF 1900 - 190F 1910 - 193F 1940 - 194F 1950 - 1FFF
RX FRAMER BERT UNUSED TX FRAMER UNUSED LIU UNUSED RX CELL/PKT PROCESSOR POS/PHY GEN UNUSED RX FIFO UNUSED TX CELL/PKT PROCESSOR UNUSED TX FIFO UNUSED GLOBAL REGISTERS (not per port) UNUSED RX SYSTEM (not per port) UNUSED TX SYSTEM (not per port) UNUSED
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11 REGISTER MAPS AND DESCRIPTIONS
11.1 Global Registers Table 11-1 Global Register Map
ADDRESS NAME
1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 180A 180B 180C 180D 180E 180F 1810 1811 1812 - 18FF
IDR GCR1 GCR2 GCR3 GCR4 GCR5 GCCR GSRR GRTPFS GSR1 GSR2 GSR3 GSR4 GSRL4 GIM1 GIM2 GIM3 GIM4 --
FUNCTION Device ID Register Global Control Register 1 Global Control Register 2 Global Control Register 3 Global Control Register 4 Global Control Register 5 Global Clock Control Register Global Software Reset Register Global RCHMRK and TCHMRK Pin Function Select Register Global Status Register 1 Global Status Register 2 Global Status Register 3 Global Status Register 4 Global Status Register Latched 4 Global Interrupt Mask Register 1 Global Interrupt Mask Register 2 Global Interrupt Mask Register 3 Global Interrupt Mask Register Latched 4 Unused. Must be set = 0 for proper operation.
11.1.1 Global Control Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 ID7 0
IDR Device Identification Register 1800
6 ID6 0
5 ID5 0
4 ID4 0
3 ID3 0
2 ID2 0
1 ID1 0
0 ID0 0
Bits 7 to 4 : Device ID (ID7 to ID4) The upper four bits of the IDR are used to display the DS26556 ID. Bits 3 to 0 : Chip Revision Bits (ID3 to ID0) The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. DEVICE DS26556 ID (ID7 to ID4) 0000
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 SIW1 0
GCR1 Global Control Register 1 1801
6 SIW0 0
5 SIM1 0
4 SIM0 0
3 DIREN 0
2 RST 0
1 RSTDP 0
0 GRST 0
Bits 7 to 6 : System Interface Bus Width (SIW[1:0]) These bits configure the system bus width. 00 = 8 bit 01 = 16 bit Bits 5 to 4 : System Interface Mode1 & 0 (SIM[1:0]) These bits configure the system bus mode. 00 = UTOPIA II 01 = UTOPIA 3 10 = POS-PHY II 11 = POS-PHY 3 Bit 3 : Direct Status Enable (DIREN) This bit selects between the direct status and polled status modes for UTOPIA and POS-PHY. 0 = Polled status mode 1 = Direct status mode Bit 2 : (RST) When this bit is set, all of the UTOPIA/POS-PHY internal data path and status and control registers on all ports will be reset to their default state. This bit must be set high for a minimum of 100ns. 0 = Normal operation. 1 = Force all internal registers to their default values Bit 1 : (RSTDP) When this bit is set, it will force all of the UTOPIA/POS-PHY internal data path registers in the to their default state. This bit must be set high for a minimum of 100ns. 0 = Normal operation. 1 = Force all framer data path registers to their default values. Bit 0 : Global Reset (GRST) When this bit is set, all of the internal data path and status and control registers of the DS26556, on all ports, will be reset to their default state. This bit must be set high for a minimum of 100ns. 0 = Normal operation. 1 = Force all internal registers to their default values.
.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
GCR2 Global Control Register 2 1802
6 0
5 0
4 0
3 0
2 BPMU 0
1 GPMU 0
0 TMEI 0
Bits 7 to 3 : Unused. Must be set = 0 for proper operation. Bit 2 : BERT Performance Monitor Register Update (BPMU) This bit is used to update all of the performance monitor registers (BERT) configured to use this bit. The performance registers configured to use this signal will be updated when this bit is toggled low to high, and the counters will be reset. The bit should remain high until the performance register update status bit goes high, then it should be brought back low which clears the PMS status bit. Bit 1 : Global Performance Monitor Register Update (GPMU) This bit is used to update all of the performance monitor registers configured to use this bit. The performance registers configured to use this signal will be updated when this bit is toggled low to high with the latest count value, and the counters will be reset. The bit should remain high until the performance register update status bit goes high, then it should be brought back low which clears the PMS status bit. Bit 0 : Transmit Manual Error Insert (TMEI) This bit is used insert an error in all ports and error insertion logic configured for global error insertion. An error(s) is inserted at the next opportunity when this bit transitions from low to high.
Register Name: Register Description: Address (hex): Bit # Name Default 7 0 6 0
GCR3 Global Control Register 3 1803
5 0
4 0
3 UPBWE 0
2 LIUBWE 0
1 BTBWE 0
0 FRBWE 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : UTOPIA/POS-PHY Bulk Write Enable (UPBWE) This bit enables the UTOPIA/POS-PHY bulk write mode. When this bit is set, a write to the register in the Cell/Packet interface of any port will write to the same register in all ports. Reading the registers of any port is not supported and will read back undefined data. Bit 2 : LIU Bulk Write Enable (LIUBWE) This bit enables the LIU bulk write mode. When this bit is set, a write to the register of any LIU will write to the same register in all the LIUs. Reading the registers of any LIU is not supported and will read back undefined data. Bit 1 : BERT Bulk Write Enable (BTBWE) This bit enables the BERT bulk write mode. When this bit is set, a write to the register of any BERT will write to the same register in all BERTs. Reading the registers of any BERT is not supported and will read back undefined data. Bit 0 : Framer Bulk Write Enable (FRBWE) This bit enables the framer bulk write mode. When this bit is set, a write to the register of any framer will write to the same register in all the framers. Reading the registers of any framer is not supported and will read back undefined data.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 IBOMS1 0
GCR4 Global Control Register 4 1804
6 IBOMS0 0
5 BPCLK1 0
4 BPCLK0 0
3 RF/RMSYN C 0
2 RLOF/ LOTC 0
1 GCLE 0
0 GIPI 0
Bits 7 to 6 : Interleave Bus Operation Mode Select (IBOMS[1:0]) These bits determine the configuration of the IBO/Estore (interleaved bus/Elastic Store) multiplexer. These bits should be used in conjunction with the Rx and Tx IBO and ESTORE control registers within each of the framer units. IBOMS1 0 0 1 1 IBOMS0 0 1 0 1 Devices Disabled 1 2 4
Bit 5 to 4 : Backplane Clock Select (BPCLK[1:0]) These bits determine the clock frequency output on the BPCLK pin. BPCLK1 0 0 1 1 BPCLK0 0 1 0 1 BP Freq 2.048 4.096 8.192 8.192
Bit 3 : Receive Frame/Multiframe Sync Select (RF/RMSYNC) This bit controls the function of all four RFSYNC/RMSYNC pins. 0 = RF/RMSYNC pins output RFSYNC. 1 = RF/RMSYNC pins output RMSYNC. Bit 2 : Receive Loss of Frame / Loss of transmit clock (RLOF/LOTC) This bit controls the function of all four RLOF/LOTC pins. 0 = RLOF/LOTC pins output RLOF(1-4) (Receive Loss of Frame) 1 = RLOF/LOTC pins output LOTC(1-4) (Loss of Transmit clock) Bit 1 : Global Counter Latch Enable (GCLE) A low to high transition on this bit will, when enabled, latch the framer performance monitor counters. Each framer can be independently enabled to accept this input. Must be cleared and set again to perform another counter latch. The counters in the cell / packet interface block cannot be latched from this bit. Bit 0 : Global Interrupt Pin Inhibit (GIPI) 0 = Normal Operation - interrupt pin (INT_B) will toggle low on an un-masked interrupt condition 1 = Interrupt Inhibit - interrupt pin (INT_B) is forced high (inactive) when this bit is set.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 IBEN4 0
GCR5 Global Control Register 5 1805
6 IBEN3 0
5 IBEN2 0
4 IBEN1 0
3 0
2 SSEL1 0
1 SSEL0 0
0 SYNCIO 0
Bit 7 : IBO Enable 4 (IBOEN4) This bit is used to determine if framer 4 is part of the IBO bus. 0 = Framer 4 is not enabled for IBO. 1 = Framer 4 is enabled for IBO. Bit 6 : IBO Enable 3 (IBOEN3) This bit is used to determine if framer 3 is part of the IBO bus. 0 = Framer 3 is not enabled for IBO. 1 = Framer 3 is enabled for IBO. Bit 5 : IBO Enable 2 (IBOEN2) This bit is used to determine if framer 2 is part of the IBO bus. 0 = Framer2 is not enabled for IBO. 1 = Framer2 is enabled for IBO. Bit 4 : IBO Enable 1 (IBOEN1) This bit is used to determine if framer1 is part of the IBO bus. 0 = Framer 1 is not enabled for IBO. 1 = Framer 1 is enabled for IBO. Bit 3 : Unused. Must be set = 0 for proper operation. Bits 2 to 1 : HSSYNC Select (HSEL[1:0]) When SYNCIO is low, these bits are used to determine which framer drives the sync pulse. HSEL1 0 0 1 1 HSEL0 0 1 0 1 Framer FR1 FR2 FR3 FR4
Bit 0 : HSSYNC I/O Select (HSSYNCIO) 0 = HSSYNC is an output. One of the framers' RSYNC signal (based on HSEL[1:0]) is used as the sync pulse for IBO mode. 1 = HSSYNC is an input. External frame sync is used as the sync pulse for IBO mode.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
GCCR Global Clock Control Register 1806
6 BPREF2 0
5 BPREF1 0
4 BPREF0 0
3 BPFREQ 0
2 MFREQ 0
1 MPS1 0
0 MPS0 0
Bit 7 : Unused. Must be set = 0 for proper operation. Bits 6 to 4 : Backplane Reference Clock Select (BPREF[2:0]) This is used to select the reference clock for BPCLK generation. The BPCLK can be generated from any of the LIU recovered clocks, external reference or derivatives of MCLK input. BPREFSEL[2:0] 000 000 001 001 010 010 011 011 BP Ref Clock Select T1 LIU RCLK1 E1 LIU RCLK1 T1 LIU RCLK2 E1 LIU RCLK2 T1 LIU RCLK3 E1 LIU RCLK3 T1 LIU RCLK4 E1 LIU RCLK4 1.544MHz derived from MCLK. Designates REFCLK to be an output and outputs 1.544MHz. 2.048MHz derived from MCLK. Designates REFCLK to be an output and outputs 2.048MHz External REFCLK. Designates REFCLK to be an input (either 1.544MHz or 2.048MHz) BPFREQ 1 0 1 0 1 0 1 0
100 101 110
1 0 1 or 0
Bit 3 : Backplane Reference Frequency Select (BPFREQ) In conjunction with BPREF[2:0], this bit selects the Reference Clock frequency for the DS26556 Backplane. 0 = Backplane Reference Clock (determined by BPREFSEL[2:0]) is 2.048MHz. 1 = Backplane Reference Clock (determined by BPREFSEL[2:0]) is 1.544MHz Note that the setting of this bit should match the T1/E1 selection for the LIU whose recovered clock is being used to generate the Backplane clock. Bit 2 : MCLK Frequency Selection (MFREQ) This bit selects the external MCLK frequency for the DS26556. 0 = MCLK input is 2.048MHz or a multiple thereof. 1 = MCLK input is 1.544MHz or a multiple thereof.
Each of the LIU Framers can be selected for T1/J1 or E1 operation.
BitS 1 to 0 : Master Period Select (MPS[1:0]) In conjunction with the MFREQ bit, these bits select the external MCLK frequency for the DS26556. MPS1 0 0 1 1 0 0 1 1 MPS0 0 1 0 1 0 1 0 1 Frequency (MHz) 1.544 3.088 6.176 12.352 2.048 4.096 8.192 16.384 MFREQ 1 1 1 1 0 0 0 0
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default
GSRR Global Software Reset Register 1807
7
LRST4 0
6
LRST3 0
5
LRST2 0
4
LRST1 0
3
FBRST4 0
2
FBRST3 0
1
FBRST2 0
0
FBRST1 0
Bit 7 to 4 : LIU Software Resets for Ports 1-4 (LRST[4:1]) 0 = Normal Operation 1 = Resets the LIU Bits 3 to 0 : Framer/BERT Software Resets for Ports 1-4 (FBRST[4:1]) 0 = Normal Operation 1 = Resets the Framer/BERT
Register Name: Register Description: Address (hex): Bit # Name Default
GRTPFS Global RCHMRK and TCHMRK Pin Function Select Register 1807
7
P4TFS 0
6
P3TFS 0
5
P2TFS 0
4
P1TFS 0
3
P4RFS 0
2
P3RFS 0
1
P2RFS 0
0
P1RFS 0
Bit 7 : Port 4 TCHMRK Pin Function Select (P4TFS) 0 = TCHMRK in cell/packet mapping mode. 1 = TCHMRK in channel clock mode. Bit 6 : Port 3 TCHMRK Pin Function Select (P3TFS) 0 = TCHMRK in cell/packet mapping mode. 1 = TCHMRK in channel clock mode. Bit 5 : Port 2 TCHMRK Pin Function Select (P2TFS) 0 = TCHMRK in cell/packet mapping mode. 1 = TCHMRK in channel clock mode. Bit 4 : Port 1 TCHMRK Pin Function Select (P1TFS) 0 = TCHMRK in cell/packet mapping mode. 1 = TCHMRK in channel clock mode. Bit 3 : Port 4 RCHMRK Pin Function Select (P4RFS) 0 = RCHMRK in cell/packet mapping mode. 1 = RCHMRK in channel clock mode. Bit 2 : Port 3 RCHMRK Pin Function Select (P3RFS) 0 = RCHMRK in cell/packet mapping mode. 1 = RCHMRK in channel clock mode. Bit 1 : Port 2 RCHMRK Pin Function Select (P2RFS) 0 = RCHMRK in cell/packet mapping mode. 1 = RCHMRK in channel clock mode. Bit 0 : Port 1 RCHMRK Pin Function Select (P1RFS) 0 = RCHMRK in cell/packet mapping mode. 1 = RCHMRK in channel clock mode.
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11.1.2 Global Status Registers
Register Name: Register Description: Address (hex): Bit # Name Default
7 BIS4 0 GSR1 Global Status Register 1 1809 6 BIS3 0 5 BIS2 0 4 BIS1 0 3 FIS4 0 2 FIS3 0 1 FIS2 0 0 FIS1 0
Bit 7 : BERT Interrupt Status 4 (BIS4) 0 = Bert 4 has not issued an interrupt 1 = Bert 4 has issued an interrupt Bit 6 : BERT Interrupt Status 3 (BIS3) 0 = Bert 3 has not issued an interrupt 1 = Bert 3 has issued an interrupt Bit 5 : BERT Interrupt Status 2 (BIS2) 0 = Bert 2 has not issued an interrupt 1 = Bert 2 has issued an interrupt Bit 4 : BERT Interrupt Status 1 (BIS1) 0 = Bert 1 has not issued an interrupt 1 = Bert 1 has issued an interrupt Bit 3 : Framer Interrupt Status 4 (FIS4) 0 = Framer 4 has not issued an interrupt 1 = Framer 4 has issued an interrupt Bit 2 : Framer Interrupt Status 3 (FIS3) 0 = Framer 3 has not issued an interrupt 1 = Framer 3 has issued an interrupt Bit 1 : Framer Interrupt Status 2 (FIS2) 0 = Framer 2 has not issued an interrupt 1 = Framer 2 has issued an interrupt Bit 0 : Framer Interrupt Status 1 (FIS1) 0 = Framer 1 has not issued an interrupt 1 = Framer 1 has issued an interrupt
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default
7 BIM4 0
GIMR1 Global Interrupt Mask Register 1 180E 5 BIM2 0 4 BIM1 0 3 FIM4 0 2 FIM3 0 1 FIM2 0 0 FIM1 0
6 BIM3 0
Bit 7 : BERT Interrupt Mask 4 (BIM4) 0 = interrupt masked 1 = interrupt enabled Bit 6 : BERT Interrupt Mask 3 (BIM3) 0 = interrupt masked 1 = interrupt enabled Bit 5 : BERT Interrupt Mask 2 (BIM2) 0 = interrupt masked 1 = interrupt enabled Bit 4 : BERT Interrupt Mask 1 (BIM1) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Framer Interrupt Mask 4 (FIM4) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Framer Interrupt Mask 3 (FIM3) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Framer Interrupt Mask 2 (FIM2) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Framer Interrupt Mask 1 (FIM1) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default
7 UPIS4 0
GSR2 Global Status Register 2 180A 6 UPIS3 0 5 UPIS2 0 4 UPIS1 0 3 LIS4 0 2 LIS3 0 1 LIS2 0 0 LIS1 0
Bit 7 : UTOPIA/POS-PHY Interrupt Status 4 (UPIS4) 0 = UTOPIA/POS-PHY Port 4 has not issued an interrupt 1 = UTOPIA/POS-PHY Port 4 has issued an interrupt Bit 6 : UTOPIA/POS-PHY Interrupt Status 3 (UPIS3) 0 = UTOPIA/POS-PHY Port 3 has not issued an interrupt 1 = UTOPIA/POS-PHY Port 3 has issued an interrupt Bit 5 : UTOPIA/POS-PHY Interrupt Status 2 (UPIS2) 0 = UTOPIA/POS-PHY Port 2 has not issued an interrupt 1 = UTOPIA/POS-PHY Port 2 has issued an interrupt Bit 4 : UTOPIA/POS-PHY Interrupt Status 1 (UPIS1) 0 = UTOPIA/POS-PHY Port 1 has not issued an interrupt 1 = UTOPIA/POS-PHY Port 1 has issued an interrupt Bit 3 : LIU Interrupt Status 4 (LIS4) 0 = LIU 4 has not issued an interrupt 1 = LIU 4 has issued an interrupt Bit 2 : LIU Interrupt Status 3 (LIS3) 0 = LIU 3 has not issued an interrupt 1 = LIU 3 has issued an interrupt Bit 1 : LIU Interrupt Status 2 (LIS2) 0 = LIU 2 has not issued an interrupt 1 = LIU 2 has issued an interrupt Bit 0 : LIU Interrupt Status 1 (LIS1) 0 = LIU 1 has not issued an interrupt 1 = LIU 1 has issued an interrupt
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default
7 UPIM4 0
GIMR2 Global Interrupt Mask Register 2 180F 6 UPIM3 0 5 UPIM2 0 4 UPIM1 0 3 LIM4 0 2 LIM3 0 1 LIM2 0 0 LIM1 0
Bit 7 : UTOPIA/POS-PHY Interrupt Mask 4 (UPIM4) 0 = interrupt masked 1 = interrupt enabled Bit 6 : UTOPIA/POS-PHY Interrupt Mask 3 (UPIM3) 0 = interrupt masked 1 = interrupt enabled Bit 5 : UTOPIA/POS-PHY Interrupt Mask 2 (UPIM2) 0 = interrupt masked 1 = interrupt enabled Bit 4 : UTOPIA/POS-PHY Interrupt Mask 1 (UPIM1) 0 = interrupt masked 1 = interrupt enabled Bit 3 : LIU Interrupt Mask 4 (LIM4) 0 = interrupt masked 1 = interrupt enabled Bit 2 : LIU Interrupt Mask 3 (LIM3) 0 = interrupt masked 1 = interrupt enabled Bit 1 : LIU Interrupt Mask 2 (LIM2) 0 = interrupt masked 1 = interrupt enabled Bit 0 : LIU Interrupt Mask 1 (LIM1) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default
GSR3 Global Status Register 3 180B
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 TSSR
0
Bit 7 - 1: Unused. Bit 0 : Transmit System Interface Status Register Interrupt Status (TSSR) This bit is set when any of the latched status register bits in the transmit system interface of the POS/PHY block are set and enabled for interrupt.
Register Name: Register Description: Address (hex): Bit # Name Default
7
GIMR3 Global Interrupt Mask Register 3 1810 6 5 4 3 2 1 0 TSSR 0
0
0
0
0
0
0
0
Bit 7 - 1: Unused. Must be set = 0 for proper operation. Bit 0 : Transmit System Interface Status Register Interrupt Mask (TSSR) 0 = interrupt masked 1 = interrupt enabled
Register Name: Register Description: Address (hex): Bit # Name Default
GSR4 Global Status Register 4 180C
7 0
6 0
5 0
4 0
3 0
2 0
1 BPMS
0
0 GPMS
0
Bit 7 - 2: Unused Bit 1 : BERT Performance Monitoring Update Status (BPMS) This bit is set when all of the port performance register update status bits (BERT PMS) are set. It is an AND of all the BERT port PMU status bits. Bit 0 : Global Performance Monitoring Update Status (GPMS) This bit is set when all of the port performance register update status bits (PSR:PMU), that are enabled for global update control (PCR2:PMUM=1), are set. It is an AND of all the globally enabled port PMU status bits. In global software update mode, the global update request bit (GCR:GPMU) should be held high until this status bit goes high.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default
GSRL4 Global Status Register Latched 4 180D
7 0
6 0
5 0
4 0
3 0
2 0
1 BPMS
0
0 GPMS
0
Bit 7 - 2: Unused. Bit 1 : BERT Performance Monitoring Update Status (BPMS) This bit is set when all of the port performance register update status bits (BERT PMS) are set. It is an AND of all the BERT port PMU status bits. Bit 0 : Global Performance Monitoring Update Status (GPMS) This bit is set when all of the port performance register update status bits (PSR:PMU), that are enabled for global update control (PCR2:PMUM=1), are set. It is an AND of all the globally enabled port PMU status bits. In global software update mode, the global update request bit (GCR:GPMU) should be held high until this status bit goes high.
Register Name: Register Description: Address (hex): Bit # Name Default
7
GIMR4 Global Interrupt Mask Register 4 1811 6 5 4 3 2 1 BPMS 0 0 GPMS 0
0
0
0
0
0
0
Bit 7 - 2: Unused. Must be set = 0 for proper operation. Bit 1 : BERT Performance Monitoring Update Status (BPMS) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Global Performance Monitoring Update Status (GPMS) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2 Cell / Packet Register Descriptions
The register descriptions are divided into separate register block sections. Bits that are underlined are read-only; all other bits are read-write. Configuration registers and bits can be written to and read from during a data path reset (LDRST bit = 0), however, all changes to these bits will be ignored during the data path reset. As a result, all bits requiring a 0 to 1 transition to initiate an action must have the transition occur after the data path reset has been removed. All counters stop counting at their maximum count. A counter register is updated by asserting (low to high transition) the associated performance monitoring update signal (xxPMU). During the counter register update process, the associated performance monitoring status signal (xxPMS) will be deasserted. The counter register update process consists of loading the counter register with the current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then asserting xxPMS. No events shall be missed during an update procedure. A latched bit is set when the associated event occurs, and remains set until it is cleared. Once cleared, a latched bit will not be set again until the associated event reoccurs (goes away and comes back). A latched on change bit is a latched bit that is set when the event occurs, and when it goes away. A latched status bit is cleared when the register is selected (register addressed and associated BSxx high), the appropriate byte enable (LBE or UBE) is high, a logic one is present on the corresponding DI[x], and the LSRCK signal goes high.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.1 General Cell / Packet Registers
Table 11-2 General Cell / Packet Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 104A 104B - 104F
NAME
FUNCTION
CPC1 CPC2 CPIS CPPMS CPPMIE -
Unused. Must be set = 0 for proper operation. CELL / PACKET Control 1 CELL / PACKET Control 2 Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. CELL / PACKET Interrupt Status CELL / PACKET Performance Monitor Status Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. CELL / PACKET Performance Monitor Interrupt Enable Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RCDV8 0
CPC1 CELL / PACKET Control 1 1041, 1241, 1441, 1641
6 -0
5 PMCPE 0
4 SYSLBK 0
3 PMUM 0
2 PMU 0
1 LDRST 0
0 LRST 0
Bit 7 : Receive ATM Cell Delineation Verify 8 enable (RCDV8) This bit determines the number of good cells required for the ATM cell delineator state machine to transition from the #Verify# state to the #Update# state. 0 = Six valid ATM cells are required (typical for framed cells) 1 = Eight valid ATM cells are required (typical for unframed cells) Bit 6 : Reserved. Must be set to 0 for proper operation. Bit 5 : POS-PHY Mode Cell Processor Enable (PMCPE) This bit determines the associated transmit and receive port interface processing (cell/packet) to be performed in the POS-PHY mode. It is only active in POS-PHY mode. 0 = Packet processing will be performed 1 = Cell processing will be performed Bit 4 : System Loopback (SYSLBK) This signal determines if cells/packets for the associated port are looped back to the system interface. When SYSLBK is low, the incoming cells/packets from the transmit FIFO are passed on to transmit cell/packet processor. When SYSLBK is high, the incoming cells/packets from the transmit FIFO are looped back to the receive FIFO. The transmit cell/packet processor outputs idle cells/inter-frame fill. This is an asynchronous signal. Bit 3 : Performance Monitor Update Mode (PMUM) This bit selects the method of updating the performance monitor registers. The global updates are controlled by the GCR2[1] bit. 0 = Port software update 1 = Global update Bit 2 : Performance Monitor Register Update (PMU) This bit is used to update all of the performance monitor registers configured to use this bit when PCR1:PMUM=0. The performance registers configured to use this signal will be updated when this bit is toggled low to high with the latest count value, and the counters reset. The bit should remain high until the performance register update status bit (PSR:PMS) goes high, then it should be brought back low which clears the PMS status bit. Bit 1 : (LDRST) When this bit is set, it will force all of the internal data path registers clocked by RSCK and TSCK pins in the corresponding cell / packet interface port to their default state. This bit must be set high for a minimum of 100ns. 0 = Normal operation. 1 = Force all data path registers to their default values. Bit 0 : (LRST) When this bit is set, all of the internal data path and status and control registers in the cell / packet interface, associated with line, will be reset to their default state for that port. This bit must be set high for a minimum of 100ns. 0 = Normal operation. 1 = Force all internal registers to their default values.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
CPC2 CELL / PACKET Control 2 1042, 1242, 1442, 1642
6 0
5 0
4 0
3 0
2 0
1
0
TBYT
0
RBYT
0
Bit 1 : Transmit Byte Synchronous Mode (TBYT) This signal determines the transmit physical interface bit/byte synchronous mode. When TBYT is high, the transmit physical interface will operate in byte synchronous mode (also known as octet aligned). When TBYT is low, the transmit physical interface will operate in bit synchronous mode. Bit 0 : Receive Byte Synchronous Mode (RBYT) This signal determines the receive physical interface bit/byte synchronous mode. When RBYT is high, the receive physical interface will operate in byte synchronous mode (also known as octet aligned). When RBYT is low, the receive physical interface will operate in bit synchronous mode.
11.2.2 Cell/Packet Status Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 0 0
CPIS CELL / PACKET Interrupt Status 1045, 1245, 1445, 1645
6 -
5 0
4 0
3 0
2 SFSR 0
1 CPSR 0
0 PMS 0
Bit 2 : System FIFO Status Register Interrupt Status (SFSR) This bit is set when any of the latched status register bits, that are enabled for interrupt, in either the transmit or receive FIFO block are set. The interrupt pin will be driven when this bit is set and the GCR4.GIPI is set to zero. (INTRF[x] || INTTF[x]) Bit 1 : Cell/Packet Status Register Interrupt Status (CPSR) This bit is set when any of the latched status register bits, that are enabled for interrupt, in the active transmit or receive cell processor or packet processor block are set. The interrupt pin will be driven when this bit is set and the GCR4.GIPI is set to zero. (INTRCP[x] || INTTCP[x]) Bit 0 : Performance Monitoring Update Status (PMS) This bit indicates the status of all active performance monitoring register and counter update signals in this port. It is an #AND# of all update status bits and is not set until all performance registers are updated and the counters reset. In software update modes, the update request bit PCR:PMU should be held high until this status bit goes high. 0 = The associated update request signal is low. 1 = The requested performance register updates are all completed.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
CPPMS CELL / PACKET Performance Monitor Status 1046, 1246, 1446, 1646
6 0
5 0
4 0
3 0
2 0
1 0
0 PMSL 0
Bits 7 - 1 : Unused Bit 0 : Performance Monitoring Update Status Latched (PMSL) This bit will be set when the PISR:PMS status bit changes from low to high. The GSR2:UPIS[x] bit will be set when this bit is set and the PSRIE:PMSIE bit is set and INT pin will be driven low when GCR4.GIPI is also set to zero.
Register Name: Register Description: Address (hex): Bit # Name Default 7 0
CPPMIE CELL / PACKET Performance Monitor Interrupt Enable 104A, 124A, 144A, 164A
6 0
5 0
4 0
3 0
2 0
1 0
0 PMSIE 0
Bits 7 - 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Performance Monitoring Update Latched Status Interrupt Enable (PMSIE) The interrupt pin will be driven when this bit is set and the PSRL:PMSL bit is set and the bit in GCR4.GIPI is set to zero.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.3 Transmit FIFO Registers
Figure 11-1 Transmit FIFO Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 118A 118B - 118F
NAME
FUNCTION
TFC TFLC1 TFLC2 TFPAC TFSRL TFSRIE -
Transmit FIFO Control Register Unused. Must be set = 0 for proper operation. Transmit FIFO Level Control Register 1 Transmit FIFO Level Control Register 2 Transmit FIFO Port Address Control Register Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Transmit FIFO Status Register Latched Unused. Must be set = 0 for proper operation. Transmit FIFO Status Register Interrupt Enable Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TFC Transmit FIFO Control Register 1180, 1380, 1580, 1780
5 -0
4 -0
3 -0
2 -0
1 -0
0 TFRST 1
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Transmit FIFO Reset (TFRST) - When 0, the Transmit FIFO will resume normal operations, however, data is discarded until a start of packet/cell is received after RAM power-up is completed. When 1, the Transmit FIFO is emptied, any transfer in progress is halted, the FIFO RAM is powered down, the associated TDXA is forced low, and all incoming data is discarded. If the port was selected when the reset was initiated, the port will be deselected, and must be reselected (TEN deasserted with address on TADR or TSX asserted with address on TDAT) before any transfer will occur.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TFLC1 Transmit FIFO Level Control Register 1 1182, 1382, 1582, 1782
5 TFAF5 0
4 TFAF4 1
3 TFAF3 0
2 TFAF2 0
1 TFAF1 0
0 TFAF0 0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation. Bits 5 to 0 : Transmit FIFO Almost Full Level (TFAF[5:0]) - In POS-PHY packet processing mode, these six bits indicate the maximum number of four byte groups that can be available in the Transmit FIFO for it to be considered "almost full". E.g., a value of 30 (1Eh) results in the FIFO being "almost full" when it has 120 (78h) bytes or less available. In cell processing mode, TFAE[5:2] are ignored, and TFAE[1:0] indicate the maximum number of cells that can be available in the Transmit FIFO for it to be considered "almost full".
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TFLC2 Transmit FIFO Level Control Register 2 1183, 1383, 1583, 1783
5 TFAE5 0
4 TFAE4 1
3 TFAE3 0
2 TFAE2 0
1 TFAE1 0
0 TFAE0 0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Transmit FIFO Almost Empty Level (TFAE[5:0]) - In POS-PHY packet processing mode, these six bits indicate the maximum number of four byte groups that can be stored in the Transmit FIFO for it to be considered "almost empty". E.g., a value of 30 (1Eh) results in the FIFO being "almost empty" when it contains 120 (78h) bytes or less. In cell processing mode, these bits are ignored.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TPA7 0 6 TPA6 0
TFPAC Transmit FIFO Port Address Control Register 1184, 1384, 1584, 1784
5 TPA5 0
4 TPA4 0
3 TPA3 0
2 TPA2 0
1 TPA1 0
0 TPA0 0
Bits 7 to 0 : Transmit FIFO System Port Address (TPA[7:0]) - These eight bits set the Transmit FIFO system interface port address used to poll the Transmit FIFO for fill status, and select it for data transfer. In Level II mode, bits TPA[7:5] are ignored, and if bits TPA[4:0] are set to a value of 1Fh, the port is disabled.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TFSRL Transmit FIFO Status Register Latched 1188, 1388, 1588, 1788
5 -0
4 TFATL 0
3 TFSTL 0
2 TFITL 0
1 TFUL 0
0 TFOL 0
Bits 7 to 5 : Unused. Bit 4 : Transmit FIFO Aborted Transfer Latched (TFATL) - This bit is set when a transfer is aborted. An aborted transfer does not occur in UTOPIA mode. In POS-PHY mode, an aborted transfer occurs when a packet error (a transfer with TERR and TEOP asserted) occurs. An aborted transfer is stored in the transmit FIFO with an abort indication. Bit 3 : Transmit FIFO Short Transfer Latched (TFSTL) - This bit is set when a "short transfer" is received. In UTOPIA mode, a "short transfer" occurs when a start of cell (a transfer with TSOC asserted) occurs before the previous cell transfer has been completed. In POS-PHY mode, a "short transfer" occurs when a start of packet (a transfer with TSOP asserted) occurs after a previous start of packet, but before an end of packet (a transfer with TEOP asserted). In UTOPIA mode, the short transfer data is discarded. In POS-PHY mode, a short transfer is stored in the transmit FIFO with an abort indication. Bit 2 : Transmit FIFO Invalid Transfer Latched (TFITL) - This bit is set when an "invalid transfer" is initiated. In UTOPIA mode, an "invalid transfer" occurs when additional cell data is transferred after the last transfer of a cell and before a transfer with TSOC asserted. In POS-PHY mode, an "invalid transfer" occurs when packet data is transferred after an end of packet, but before a start of packet (this includes another end of packet transfer). The invalid transfer data is discarded. Bit 1 : Transmit FIFO Underflow Latched (TFUL) - This bit is set when a Transmit FIFO underflow condition occurs. An underflow condition results in a loss of data. Bit 0 : Transmit FIFO Overflow Latched (TFOL) - This bit is set when a Transmit FIFO overflow condition occurs. An overflow condition results in a loss of data.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TFSRIE Transmit FIFO Status Register Interrupt Enable 118A, 138A, 158A, 178A
5 -0
4 TFATIE 0
3 TFSTIE 0
2 TFITIE 0
1 TFUIE 0
0 TFOIE 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Transmit FIFO Aborted Transfer Interrupt Enable (TFATIE) - This bit enables an interrupt if the TFATL bit in the TFSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 3 : Transmit FIFO Short Transfer Interrupt Enable (TFSTIE) - This bit enables an interrupt if the TFSTL bit in the TFSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 2 : Transmit FIFO Invalid Transfer Interrupt Enable (TFITIE) - This bit enables an interrupt if the TFITL bit in the TFSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 1 : Transmit FIFO Underflow Interrupt Enable (TFUIE) - This bit enables an interrupt if the TFUL bit in the TFSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 0 : Transmit FIFO Overflow Interrupt Enable (TFOIE) - This bit enables an interrupt if the TFOL bit in the TFSRL register is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.4 Transmit Cell Processor Registers
Table 11-3 Transmit Cell Processor Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 110A 110B 110C 110D 110E 110F 1110 1111 1112 1113 1114 1115 1116 1117-111F
NAME
FUNCTION
TCPC1 TCPC2 TECC1 TECC2 THMRC THPC1 THPC2 THPC3 THPC4 TFPPC TCPSR TCPSRL TCPSRIE TCCR1 TCCR2 TCCR3 -
Transmit Cell Processor Control Register 1 Transmit Cell Processor Control Register 2 Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Transmit Errored Cell Control Register 1 Transmit Errored Cell Control Register 2 Transmit HEC Error Mask Control Register Unused. Must be set = 0 for proper operation. Transmit Header Pattern Control Register 1 Transmit Header Pattern Control Register 2 Transmit Header Pattern Control Register 3 Transmit Header Pattern Control Register 4 Transmit Fill Cell Payload Pattern Control Register Unused. Must be set = 0 for proper operation. Transmit Cell Processor Status Register Unused. Must be set = 0 for proper operation. Transmit Cell Processor Status Register Latched Unused. Must be set = 0 for proper operation. Transmit Cell Processor Status Register Interrupt Enable Unused. Must be set = 0 for proper operation. Transmit Cell Count Register 1 Transmit Cell Count Register 2 Transmit Cell Count Register 3 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TCPC1 Transmit Cell Processor Control Register 1 1100, 1300, 1500, 1700
5 TFCH 0
4 TFCP 0
3 THSE 0
2 TSD 0
1 TBRE 0
0 TCCE 0
Bits 7& 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Transmit Fill Cell Header Type (TFCH) - When 0, an idle cell header (00 00 00 01h) will be used in fill cells. When 1, a programmable header will be used in fill cells. The setting of this bit does not affect the contents of the cell payload bytes. Bit 4 : Transmit Fill Cell Payload Type (TFCP) - When 0, an idle cell payload byte (6Ah) will be used in each payload byte fill cells. When 1, a programmable cell payload byte will be used in each payload byte fill cells. The setting of this bit does not affect the contents of the cell header bytes. Bit 3 : Transmit Cell Header Scrambling Enable (THSE) - When 0, only the cell payload will be scrambled. When 1, the entire data stream (cell header and payload) is scrambled. This bit is ignored if scrambling is disabled, or DSS scrambling is enabled. When clear channel is enabled, the entire data stream will be scrambled if scrambling is enabled. Bit 2 : Transmit Scrambling Disable (TSD) - When 0, scrambling is performed. When 1, scrambling is disabled. Bit 1 : Transmit Bit Reordering Enable (TBRE) - When 0, bit reordering is disabled (The first bit transmitted is from the MSB of the transmit FIFO byte TFD[7]). When 1, bit reordering is enabled (The first bit transmitted is from the LSB of the transmit FIFO byte TFD[0]). Bit 0 : Transmit Clear Channel Enable (TCCE) - When 0, cell processing is enabled. When 1, clear channel is enabled, and all cell processing functions except scrambling and bit reordering are disabled.
Register Name: Register Description: Address (hex): Bit # Name Default 7 SPARE 0 6 -0
TCPC2 Transmit Cell Processor Control Register 2 1101, 1301, 1501, 1701
5 -0
4 -0
3 TDSE 0
2 TDHE 0
1 THPE 0
0 TCPAD 0
Bit 7 : Spare Configuration Bit (SPARE) - This bit is a spare configuration bit reserved for future use. It can be written to and read from, however it does not effect the operation of the CELL / PACKET INTERFACE. Bits 6 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Transmit DSS Scrambling Enable (TDSE) - When 0, self-synchronous scrambling is enabled. When 1, DSS scrambling is enabled. This bit is ignored if scrambling is disabled. Note: In byte synchronous and clear channel modes self-synchronous scrambling is enabled regardless of the setting of this bit. Bit 2 : Transmit DQDB HEC Processing Enable (TDHE) - When 0, the HEC is calculated over all four header bytes. When 1, only the last three header bytes are used for HEC calculation. Bit 1 : Transmit HEC Pass-through Enable (THPE) - When 0, the calculated HEC byte will overwrite the HEC byte in the cell. When 1, the HEC byte in the cell is passed through. Note: The calculated HEC is always inserted into cells that are received without a HEC byte. Bit 0 : Transmit HEC Coset Polynomial Addition Disable (TCPAD) - When 0, the HEC coset polynomial addition is performed prior to inserting the HEC byte. When 1, HEC coset polynomial addition is disabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 TCEN7 0 6 TCEN6 0
TECC1 Transmit Errored Cell Control Register 1 1104, 1304, 1504, 1704
5 TCEN5 0
4 TCEN4 0
3 TCEN3 0
2 TCEN2 0
1 TCEN1 0
0 TCEN0 0
Bits 7 to 0 : Transmit Errored Cell Insertion Number (TCEN[7:0]) - These eight bits indicate the total number of errored cells to be transmitted. A value of FFh results in continuous errored cell insertion at the specified rate. Register Name: TECC2 Register Description: Transmit Errored Cell Control Register 2 Address (hex): 1105, 1305, 1505, 1705
Bit # Name Default
7 MEIMS 0
6 TCER6 0
5 TCER5 0
4 TCER4 0
3 TCER3 0
2 TCER2 0
1 TCER1 0
0 TCER0 0
Bit 7 : Manual Error Insert Mode Select (MEIMS) - When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to a 1. Note: Enabling TMEI does not disable error insertion using TCER[6:0] and TCEN[7:0]. Bits 6 to 0 : Transmit Errored Cell Insertion Rate (TCER[6:0]) - These seven bits indicate the rate at which y errored cells are to be output. One out of every x * 10 cells is to be an errored cell. TCER[4:1] is the value x, and TCER[6:4] is the value y which has a maximum value of 6. If TCER[4:1] has a value of 0h errored cell insertion is 6 disabled. If TCER[6:4] has a value of 6xh or 7xh the errored cell rate will be x * 10 . A TCER[6:0] value of 01h th results in every cell being errored. A TCER[6:0] value of 0Fh results in every 15 cell being errored. A TCER[6:0] th value of 11h results in every 10 cell being errored. Errored cell insertion starts when the TECC register is written to with a TCER[4:1] value that is non-zero. If the TECC register is written to during the middle of an errored cell insertion process, the current process is halted, and a new process will be started using the new values of TCER[6:0] and TCEN[7:0}. Errored cell insertion ends when TCEN[7:0] errored cells have been transmitted.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 THEM7 0 6 THEM6 0
THMRC Transmit HEC Error Mask Control Register 1106, 1306, 1506, 1706
5 THEM5 0
4 THEM4 0
3 THEM3 0
2 THEM2 0
1 THEM1 0
0 THEM0 0
Bits 7 to 0 : Transmit HEC Error Mask (THEM[7:0]) - These eight bits indicate whether or not the associated HEC bit is inverted during cell error insertion. If THEM[x] is high, HEC bit x is corrupted during an errored cell. If THEM[x] is low, HEC bit x is passed uncorrupted during an errored cell. If THEM[7:0] is all zeros, error insertion is disabled. The table below indicates the type of error inserted by a specific mask value. Note: If a single bit error is inserted in the HEC, and the far-end has single bit error correction enabled, this will cause the indicated header bit to be corrupted. Value Error Type Bit Value Error Type Bit Value Error Type Bit
01h-02h 05h-06h 09h-0Ah 0Eh 11h-14h 17h-1Dh 20h 2Bh 31h 39h-3Fh 43h 52h-53h 57h 5Bh 68h-6Ah 70h 81h-85h 89h 9Ch-A1h A8h ACh-ADh B0h B7h-C6h CEh D7h-DFh
HEC Multi Multi Single Multi Multi HEC Multi Single Multi Single Multi Single Single Multi Single Multi Single Multi Single Multi Single Multi Single Multi
- - - 31 - - - - 01 - 11 - 20 18 - 28 - 25 - 21 - 05 - 03 -
03h 07h 0Bh 0Fh 15h 1Eh 21h-29h 2Ch 32h-37h 40h 44h-50h 54h 58h 5Ch-66h 6Bh 71h-7Fh 86h 90h-9Ah A2h A9h-AAh AEh B1h-B5h C7h CFh-D5h E0h
Multi Single Single Multi Single Single Multi Single Multi HEC Multi Single Single Multi Single Multi Single Multi Single Multi Single Multi Single Multi Single 123 of 362
32 09 - 24 30 - 07 - - - 22 06 - 16 - 10 - 12 - 19 - 26 - 27
04h 08h 0Ch-0Dh 10h 16h 1Fh 2Ah 2Dh-30h 38h 41h-42h 51h 55h-56h 59h-5Ah 67h 6Ch-6Fh 80h 87h-88h 9Bh A3h-A7h ABh AFh B6h C8h-CDh D6h E1h-FFh
HEC HEC Multi HEC Single Multi Single Multi Single Multi Single Multi Multi Single Multi HEC Multi Single Multi Single Multi Single Multi Single Multi
- - - - 08 - 23 - 29 - 13 - - 04 - - - 02 - 14 - 17 - 15 -
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Transmit Programmable Header Pattern (THP[31:0]) - These thirty-two bits indicate the header bit pattern to be used in the header of fill cells when the TCPC register bit TFCH is set.
Register Name: Register Description: Address (hex): Bit # Name Default 7 THP7 0 6 THP6 0
THPC1 Transmit Header Pattern Control Register 1 1108, 1308, 1508, 1708
5 THP5 0
4 THP4 0
3 THP3 0
2 THP2 0
1 THP1 0
0 THP0 0
Bits 7 to 0 : Transmit Programmable Header Pattern (THP[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 THP15 0 6 THP14 0
THPC2 Transmit Header Pattern Control Register 2 1109, 1309, 1509, 1709
5 THP13 0
4 THP12 0
3 THP11 0
2 THP10 0
1 THP9 0
0 THP8 0
Bits 7 to 0 : Transmit Programmable Header Pattern (THP[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 THP23 0 6 THP22 0
THPC3 Transmit Header Pattern Control Register 3 110A, 130A, 150A, 170A
5 THP21 0
4 THP20 0
3 THP19 0
2 THP18 0
1 THP17 0
0 THP16 0
Bits 7 to 0 : Transmit Programmable Header Pattern (THP[23:16])
Register Name: Register Description: Address (hex): Bit # Name Default 7 THP31 0 6 THP30 0
THPC4 Transmit Header Pattern Control Register 4 110B, 130B, 150B, 170B
5 THP29 0
4 THP28 0
3 THP27 0
2 THP26 0
1 THP25 0
0 THP24 0
Bits 7 to 0 : Transmit Programmable Header Pattern (THP[31:24])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TFPP7 0 6 TFPP6 0
TFPPC Transmit Fill Cell Payload Pattern Control Register 110C, 130C, 150C, 170C
5 TFPP5 0
4 TFPP4 0
3 TFPP3 0
2 TFPP2 0
1 TFPP1 0
0 TFPP0 0
Bits 7 to 0 : Transmit Fill Cell Payload Pattern (TFPP[7:0]) - These eight bits indicate the value to be placed in the payload bytes of the fill cells when the TCPC register bit TFCP is set..
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TCPSR Transmit Cell Processor Status Register 110E, 130E, 150E, 170E
5 -0
4 -0
3 -0
2 -0
1 -0
0 TECF 0
Bits 7 to 1 : Unused. Bit 0 : Transmit Errored Cell Insertion Finished (TECF) - This bit is set when the number of errored cells indicated by the TCEN[7:0] bits in the TECC register have been transmitted. This bit is cleared when errored cell insertion is disabled, or a new errored cell insertion process is initiated.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TCPSRL Transmit Cell Processor Status Register Latched 1110, 1310, 1510, 1710
5 -0
4 -0
3 -0
2 -0
1 -0
0 TECFL 0
Bits 7 to 1 : Unused. Bit 0 : Transmit Errored Cell Insertion Finished Latched (TECFL) - This bit is set when the TECF bit in the TCPSR register transitions from zero to one.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TCPSRIE Transmit Cell Processor Status Register Interrupt Enable 1112, 1312, 1512, 1712
5 -0
4 -0
3 -0
2 -0
1 -0
0 TECFIE 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Transmit Errored Cell Insertion Finished Interrupt Enable (TECFIE) - This bit enables an interrupt if the TECFL bit in the TCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Transmit Cell Count (TCC[23:0]) - These twenty-four bits indicate the number of cells extracted from the Transmit FIFO and output in the outgoing data stream.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TCC7 0 6 TCC6 0
TCCR1 Transmit Cell Count Register 1 1114, 1314, 1514, 1714
5 TCC5 0
4 TCC4 0
3 TCC3 0
2 TCC2 0
1 TCC1 0
0 TCC0 0
Bits 7 to 0 : Transmit Cell Count (TCC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 TCC15 0 6 TCC14 0
TCCR2 Transmit Cell Count Register 2 1115, 1315, 1515, 1715
5 TCC13 0
4 TCC12 0
3 TCC11 0
2 TCC10 0
1 TCC9 0
0 TCC8 0
Bits 7 to 0 : Transmit Cell Count (TCC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 TCC23 0 6 TCC22 0
TCCR3 Transmit Cell Count Register 3 1116, 1316, 1516, 1716
5 TCC21 0
4 TCC20 0
3 TCC19 0
2 TCC18 0
1 TCC17 0
0 TCC16 0
Bits 7 to 0 : Transmit Cell Count (TCC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.5 Transmit Packet Processor Registers
Table 11-4 Transmit Packet Processor Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1100 1101 1102 1103 1104 1105 1106 - 110E 110F 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 111A 111B 111C - 111F
NAME
FUNCTION
TPPC TIFGC TEPC1 TEPC2 RES TPPSR TPPSRL TPPSRIE TPCR1 TPCR2 TPCR3 TBCR1 TBCR2 TBCR3 TBCR4 -
Unused. Must be set = 0 for proper operation. Transmit Packet Processor Control Register Transmit Inter-Frame Gapping Control Register Unused. Must be set = 0 for proper operation. Transmit Errored Packet Control Register 1 Transmit Errored Packet Control Register 2 Unused. Must be set = 0 for proper operation. Transmit Packet Processor Status Register Unused. Must be set = 0 for proper operation. Transmit Packet Processor Status Register Latched Unused. Must be set = 0 for proper operation. Transmit Packet Processor Status Register Interrupt Enable Transmit Packet Count Register 1 Transmit Packet Count Register 2 Transmit Packet Count Register 3 Unused. Must be set = 0 for proper operation. Transmit Byte Count Register 1 Transmit Byte Count Register 2 Transmit Byte Count Register 3 Transmit Byte Count Register 4 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TPPC Transmit Packet Processor Control Register 1101, 1301, 1501, 1701
5 TFAD 0
4 TF16 0
3 TIFV 0
2 TSD 0
1 TBRE 0
0 TCCE 0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Transmit FCS Append Disable (TFAD) - This bit controls whether or not an FCS is appended to the end of each packet. When 0, the calculated FCS bytes are appended to the end of the packet. When 1, the packet is transmitted without an FCS. Bit 4 : Transmit FCS-16 Enable (TF16) - When 0, the FCS processing uses a 32-bit FCS. When 1, the FCS processing uses a 16-bit FCS Bit 3 : Transmit Bit Synchronous Inter-frame Fill Value (TIFV) - When 0, inter-frame fill is done with the flag sequence (7Eh). When 1, inter-frame fill is done with all '1's. This bit is ignored in byte synchronous mode. Bit 2 : Transmit Scrambling Disable (TSD) - When 0, scrambling is performed. When 1, scrambling is disabled. Bit 1 : Receive Bit Reordering Enable (RBRE) - When 0, bit reordering is disabled (The first bit transmitted is from the MSB of the transmit FIFO byte TFD[7]). When 1, bit reordering is enabled (The first bit transmitted is from the LSB of the transmit FIFO byte TFD[0]). Bit 0 : Transmit Clear Channel Enable (TCCE) - When 0, packet processing is enabled. When 1, clear channel is enabled, and all packet-processing functions except scrambling and bit reordering are disabled.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 TIFG7 0 6 TIFG6 0
TIFGC Transmit Inter-Frame Gapping Control Register 1102, 1302, 1502, 1702
5 TIFG5 0
4 TIFG4 0
3 TIFG3 0
2 TIFG2 0
1 TIFG1 0
0 TIFG0 1
Bits 7 to 0 : Transmit Inter-Frame Gapping (TIFG[7:0]) - These eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill between packets will be at least the value of TIFG[7:0] plus 1. Note: If inter-frame fill is set to all 1's, a TFIG value of 2 or 3 will result in a flag, at least two bytes of 1's, and a flag between packets.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TPEN7 0 6 TPEN6 0
TEPC1 Transmit Errored Packet Control Register 1 1104, 1304, 1504, 1704
5 TPEN5 0
4 TPEN4 0
3 TPEN3 0
2 TPEN2 0
1 TPEN1 0
0 TPEN0 0
Bits 7 to 0 : Transmit Errored Packet Insertion Number (TPEN[7:0]) - These eight bits indicate the total number of errored packets to be transmitted. A value of FFh results in continuous errored packet insertion at the specified rate.
Register Name: Register Description: Address (hex): Bit # Name Default 7 MEIMS 0 6 TPER6 0
TEPC2 Transmit Errored Packet Control Register 2 1105, 1305, 1505, 1705
5 TPER5 0
4 TPER4 0
3 TPER3 0
2 TPER2 0
1 TPER1 0
0 TPER0 0
Bit 7 : Manual Error Insert Mode Select (MEIMS) - When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to a 1. Note: Enabling TMEI does not disable error insertion using TCER[6:0] and TCEN[7:0]. Bits 6 to 0 : Transmit Errored Packet Insertion Rate (TPER[6:0]) - These seven bits indicate the rate at which y errored packets are to be output. One out of every x * 10 packets is to be an errored packet. TPER[3:0] is the value x, and TPER[6:4] is the value y which has a maximum value of 6. If TPER[3:0] has a value of 0h errored packet 6 insertion is disabled. If TPER[6:4] has a value of 6xh or 7xh the errored packet rate will be x * 10 . A TPER[6:0] th value of 01h results in every packet being errored. A TPER[6:0] value of 0Fh results in every 15 packet being th errored. A TPER[6:0] value of 11h result in every 10 packet being errored. Errored packet insertion starts when the TEPC register is written to with a TPER[3:0] value that is non-zero. If the TEPC register is written to during the middle of an errored packet insertion process, the current process is halted, and a new process will be started using the new values of TPER[6:0] and TPEN[7:0}. Errored packet insertion ends when TPEN[7:0] errored packets have been transmitted.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TPPSR Transmit Packet Processor Status Register 110F, 130F, 150F, 170F
5 -0
4 -0
3 -0
2 -0
1 -0
0 TEPF 0
Bits 7 to 1 : Unused. Bit 0 : Transmit Errored Packet Insertion Finished (TEPF) - This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TPPSRL Transmit Packet Processor Status Register Latched 1111, 1311, 1511, 1711
5 -0
4 -0
3 -0
2 -0
1 -0
0 TEPFL 0
Bits 7 to 1 : Unused. Bit 0 : Transmit Errored Packet Insertion Finished Latched (TEPFL) - This bit is set when the TEPF bit in the TPPSR register transitions from zero to one.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TPPSRIE Transmit Packet Processor Status Register Interrupt Enable 1113, 1313, 1513, 1713
5 -0
4 -0
3 -0
2 -0
1 -0
0 TEPFIE 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Transmit Errored Packet Insertion Finished Interrupt Enable (TEPFIE) - This bit enables an interrupt if the TEPFL bit in the TPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Transmit Packet Count (TPC[23:0]) - These twenty-four bits indicate the number of packets extracted from the Transmit FIFO and output in the outgoing data stream.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TPC7 0 6 TPC6 0
TPCR1 Transmit Packet Count Register 1 1114, 1314, 1514, 1714
5 TPC5 0
4 TPC4 0
3 TPC3 0
2 TPC2 0
1 TPC1 0
0 TPC0 0
Bits 7 to 0 : Transmit Packet Count (TPC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 TPC15 0 6 TPC14 0
TPCR2 Transmit Packet Count Register 2 1115, 1315, 1515, 1715
5 TPC13 0
4 TPC12 0
3 TPC11 0
2 TPC10 0
1 TPC9 0
0 TPC8 0
Bits 7 to 0 : Transmit Packet Count (TPC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 TPC23 0 6 TPC22 0
TPCR3 Transmit Packet Count Register 3 1116, 1316, 1516, 1716
5 TPC21 0
4 TPC20 0
3 TPC19 0
2 TPC18 0
1 TPC17 0
0 TPC16 0
Bits 7 to 0 : Transmit Packet Count (TPC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Transmit Byte Count (TBC[31:0]) - These thirty-two bits indicate the number of packet bytes inserted in the outgoing data stream.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TBC7 0 6 TBC6 0
TBCR1 Transmit Byte Count Register 1 1118, 1318, 1518, 1718
5 TBC5 0
4 TBC4 0
3 TBC3 0
2 TBC2 0
1 TBC1 0
0 TBC0 0
Bits 7 to 0 : Transmit Byte Count (TBC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 TBC15 0 6 TBC14 0
TBCR2 Transmit Byte Count Register 2 1119, 1319, 1519, 1719
5 TBC13 0
4 TBC12 0
3 TBC11 0
2 TBC10 0
1 TBC9 0
0 TBC8 0
Bits 7 to 0 : Transmit Byte Count (TBC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 TBC23 0 6 TBC22 0
TBCR3 Transmit Byte Count Register 3 111A, 131A, 151A, 171A
5 TBC21 0
4 TBC20 0
3 TBC19 0
2 TBC18 0
1 TBC17 0
0 TBC16 0
Bits 7 to 0 : Transmit Byte Count (TBC[23:16])
Register Name: Register Description: Address (hex): Bit # Name Default 15 TBC31 0 14 TBC30 0
TBCR4 Transmit Byte Count Register 4 111B, 131B, 151B, 171B
13 TBC29 0
12 TBC28 0
11 TBC27 0
10 TBC26 0
9 TBC25 0
8 TBC24 0
Bits 7 to 0 : Transmit Byte Count (TBC[31:24])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.6 Receive Cell Processor Registers
Table 11-5 Receive Cell Processor Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C 101D 101E 4101F 1020 1021 1022 1023 1024 1025 1026 1027-103F
NAME
FUNCTION
RCPC1 RCPC2 RHPC1 RHPC2 RHPC3 RHPC4 RHPMC1 RHPMC2 RHPMC3 RHPMC4 RLTC1 RLTC2 RCPSR1 RCPSR2 RCPSRL1 RCPSRL2 RCPSRIE1 RCPSRIE2 RCCR1 RCCR2 RCCR3 REHCR1 REHCR2 REHCR3 RHPCR1 RHPCR2 RHPCR3 RCCCR1 RCCCR2 RCCCR3 RFCCR1 RFCCR2 RFCCR3 -
Receive Cell Processor Control Register 1 Receive Cell Processor Control Register 2 Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Receive Header Pattern Control Register 1 Receive Header Pattern Control Register 2 Receive Header Pattern Control Register 3 Receive Header Pattern Control Register 4 Receive Header Pattern Mask Control Register 1 Receive Header Pattern Mask Control Register 2 Receive Header Pattern Mask Control Register 3 Receive Header Pattern Mask Control Register 4 Receive LCD Threshold Control Register 1 Receive LCD Threshold Control Register 2 Receive Cell Processor Status Register 1 Receive Cell Processor Status Register 2 Receive Cell Processor Status Register Latched 1 Receive Cell Processor Status Register Latched 2 Receive Cell Processor Register Interrupt Enable 1 Receive Cell Processor Register Interrupt Enable 2 Receive Cell Count Register 1 Receive Cell Count Register 2 Receive Cell Count Register 3 Unused. Must be set = 0 for proper operation. Receive Errored Header Count Register 1 Receive Errored Header Count Register 2 Receive Errored Header Count Register 3 Unused. Must be set = 0 for proper operation. Receive Header Pattern Cell Count Register 1 Receive Header Pattern Cell Count Register 2 Receive Header Pattern Cell Count Register 3 Unused. Must be set = 0 for proper operation. Receive Corrected Cell Count Register 1 Receive Corrected Cell Count Register 2 Receive Corrected Cell Count Register 3 Unused. Must be set = 0 for proper operation. Receive Filtered Cell Count Register 1 Receive Filtered Cell Count Register 2 Receive Filtered Cell Count Register 3 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 RROC1 0 6 RROC0 0
RCPC1 Receive Cell Processor Control Register 1 1000, 1200, 1400, 1600
5 RCPAD 0
4 RHECD 0
3 RHDE 0
2 RDD 0
1 RBRE 0
0 RCCE 0
Bit 7 & 6 : Receive Error Monitoring Required OK Cells (RROC[1:0]) - These two bits indicate the number of good cells required to transition from the "Detection" state to the "Correction" state. 00 = 1 good cell is required. 01 = 2 good cells are required. 10 = 4 good cells are required. 11 = 8 good cells are required. Bit 5 : Receive HEC Coset Polynomial Addition Disable (RCPAD) - When 0, the HEC coset polynomial addition is performed prior to checking the HEC byte. When 1, HEC coset polynomial addition is disabled Bit 4 : Receive Header Error Correction Disable (RHECD) - When 0, single bit header error correction is enabled. When 1, header error correction is disabled and all errors are treated as an uncorrectable error. Bit 3 : Receive Cell Header Descrambling Enable (RHDE) - When 0, only the cell payload will be descrambled. When 1, the entire data stream (cell header and payload) is descrambled. This bit is ignored if descrambling is disabled or DSS descrambling is enabled. When clear channel is enabled, the entire data stream will be descrambled if descrambling is enabled. Bit 2 : Receive Descrambling Disable (RDD) - When 0, descrambling is performed. When 1, descrambling is disabled. Bit 1 : Receive Bit Reordering Enable (RBRE) - When 0, bit reordering is disabled (The first bit received is stored in the MSB of the receive FIFO byte RFD[7]). When 1, bit reordering is enabled (The first bit received is stored in the LSB of the receive FIFO byte RFD[0]). Bit 0 : Receive Clear Channel Enable (RCCE) - When 0, cell processing is enabled. When 1, clear channel is enabled, and all cell processing functions except descrambling and bit reordering are disabled.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RDDE 0 6 RDHE 0
RCPC2 Receive Cell Processor Control Register 2 1001, 1201, 1401, 1601
5 RECED 0
4 RHPM1 0
3 RHPM0 0
2 RICFD 0
1 RUCFE 0
0 RICFE 0
Bit 7 : Receive DSS Descrambling Enable (RDDE) - When 0, self-synchronous descrambling is enabled. When 1, DSS descrambling is enabled. This bit is ignored if descrambling is disabled. Note: In byte synchronous and clear channel modes self-synchronous descrambling is enabled regardless of the setting of this bit. Bit 6 : Receive DQDB HEC Processing Enable (RDHE) - When 0, the HEC is calculated over all four header bytes. When 1, only the last three header bytes are used for HEC calculation. Bit 5 : Receive Errored Cell Extraction Disable (RECED) - When 0, errored cells are extracted. When 1, errored cells are passed on. Bit 4 to 3 : Receive Header Pattern Comparison Mode (RHPM[1:0]) - These two bits control the operation of the header pattern comparison function. 00 = Count match: Cells that match the header pattern are counted. 01 = Count no match - Cells that do not match the header pattern are counted. 10 = Discard match - Cells that match the header pattern are counted and discarded. 11 = Discard no match - Cells that do not match the header pattern are counted and discarded. Bit 2 : Receive Idle Cell Filtering Disable (RICFD) - When 0, idle cells are discarded. When 1, idle cells are passed on. Bit 1 : Receive Unassigned Cell Filtering Enable (RUCFE) - When 0, unassigned cells are passed on. When 1, unassigned cells are counted and discarded. Bit 0 : Receive Invalid Cell Filtering Enable (RICFE) - When 0, invalid cells are passed on. When 1, invalid cells are discarded.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Header Pattern (RHP[31:0]) - These 32 bits indicate the receive header bit pattern to be detected by the header pattern comparison function.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHP7 0 6 RHP6 0
RHPC1 Receive Header Pattern Control Register 1 1004, 1204, 1404, 1604
5 RHP5 0
4 RHP4 0
3 RHP3 0
2 RHP2 0
1 RHP1 0
0 RHP0 0
Bit 7 to 0 : Receive Header Pattern (RHP[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHP15 0 6 RHP14 0
RHPC2 Receive Header Pattern Control Register 2 1005, 1205, 1405, 1605
5 RHP13 0
4 RHP12 0
3 RHP11 0
2 RHP10 0
1 RHP9 0
0 RHP8 0
Bits 7 to 0 : Receive Header Pattern (RHP[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHP23 0 6 RHP22 0
RHPC3 Receive Header Pattern Control Register 3 1006, 1206, 1406, 1606
5 RHP21 0
4 RHP20 0
3 RHP19 0
2 RHP18 0
1 RHP17 0
0 RHP16 0
Bits 7 to 0 : Receive Header Pattern (RHP[23:16])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHP31 0 6 RHP30 0
RHPC4 Receive Header Pattern Control Register 4 1007, 1207, 1407, 1607
5 RHP29 0
4 RHP28 0
3 RHP27 0
2 RHP26 0
1 RHP25 0
0 RHP24 0
Bits 7 to 0 : Receive Header Pattern (RHP[31:24])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Header Pattern Comparison Disable (RHPD[31:0]) - These 32 bits indicate whether or not the associated header bit is checked by the header pattern comparison function. If RHPD[x] is high, the header bit x is ignored during the header pattern comparison (don't care). If RHPD[x] is low, the associated bit in the header must match RHP[x] in the receive header pattern control register RHPC.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHPD7 0 6 RHPD6 0
RHPMC1 Receive Header Pattern Mask Control Register 1 1008, 1208, 1408, 1608
5 RHPD5 0
4 RHPD4 0
3 RHPD3 0
2 RHPD2 0
1 RHPD1 0
0 RHPD0 0
Bits 7 to 0 : Receive Header Pattern Comparison Disable (RHPD[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 15 RHPD15 0
RHPMC2 Receive Header Pattern Mask Control Register 2 1009, 1209, 1409, 1609
14 RHPD14 0
13 RHPD13 0
12 RHPD12 0
11 RHPD11 0
10 RHPD10 0
9 RHPD9 0
8 RHPD8 0
Bits 7 to 0 : Receive Header Pattern Comparison Disable (RHPD[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHPD23 0
RHPMC3 Receive Header Pattern Mask Control Register 3 100A, 120A, 140A, 160A
6 RHPD22 0
5 RHPD21 0
4 RHPD20 0
3 RHPD19 0
2 RHPD18 0
1 RHPD17 0
0 RHPD16 0
Bits 7 to 0 : Receive Header Pattern Comparison Disable (RHPD[23:16])
Register Name: Register Description: Address (hex): Bit # Name Default 15 RHPD31 0
RHPMC4 Receive Header Pattern Mask Control Register 4 100B, 120B, 140B, 160B
14 RHPD30 0
13 RHPD29 0
12 RHPD28 0
11 RHPD27 0
10 RHPD26 0
9 RHPD25 0
8 RHPD24 0
Bits 7 to 0 : Receive Header Pattern Comparison Disable (RHPD[31:24])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 RLT7 0 6 RLT6 1
RLTC1 Receive LCD Threshold Control Register1 100C, 120C, 140C, 160C
5 RLT5 1
4 RLT4 0
3 RLT3 1
2 RLT2 0
1 RLT1 0
0 RLT0 0
Bits 7 to 0 : Receive LCD Threshold (RLT[7:0]) - These sixteen bits indicate the number of consecutive cell periods the cell delineation state machine must be in an Out of Cell Delineation (OCD) condition before it declares or terminate a Loss of Cell Delineation (LCD) condition. A value of 0000h causes LCD to be declared at the same time as OCD.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RLT15 0 6 RLT14 0
RLTC2 Receive LCD Threshold Control Register2 100D, 120D, 140D, 160D
5 RLT13 0
4 RLT12 0
3 RLT11 0
2 RLT10 0
1 RLT9 0
0 RLT8 1
Bits 7 to 0 : Receive LCD Threshold (RLT[15:8]) - These sixteen bits indicate the number of consecutive cell periods the cell delineation state machine must be in an Out of Cell Delineation (OCD) condition before it declares or terminate a Loss of Cell Delineation (LCD) condition. A value of 0000h causes LCD to be declared at the same time as OCD.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RCPSR1 Receive Cell Processor Status Register1 100E, 120E, 140E, 160E
5 -0
4 -0
3 -0
2 RECC 0
1 RHPC 0
0 RCHC 0
Bits 7 to 3 : Unused. Bit 2 : Receive Errored Header Cell Count (RECC) - This read only bit indicates that the receive errored header cell count is non-zero. Bit 1 : Receive Header Pattern Cell Count (RHPC) - This read only bit indicates that the receive header pattern comparison cell count is non-zero. Bit 0 : Receive Corrected Cell Count (RCHC) - This read only bit indicates that the receive corrected header cell count is non-zero.
Register Name: Register Description: Address (hex): Bit # Name Default 7 SPR 0 6 -0
RCPSR2 Receive Cell Processor Status Register2 100F, 120F, 140F, 160F
5 -0
4 -0
3 OOS 0
2 -0
1 OCD 1
0 LCD 0
Bit 7 : Spare Status Bit (SPR) - This bit is a spare status bit reserved for future use. It indicates the current value of the RCPC2.SPARE bit. Bits 6 to 4 : Unused. Bit 3 : Out Of Sync (OOS) - This read only bit indicates that a DSS Out Of Sync (OOS) state exists. DSS OOS occurs when the DSS Scrambler Synchronization state machine is in the "Load" or "Verify" state, and DSS scrambling has been enabled. Bit 2 : Unused. Bit 1 : Out Of Cell Delineation (OCD) - This read only bit indicates that an Out of Cell Delineation condition (OCD) exists. When DSS scrambling is disabled, OCD occurs when the HEC Error Monitoring state machine is in the "OCD" state. When DSS scrambling is enabled, OCD occurs when the DSS OCD Detection state machine is in the "OCD" state. Bit 0 : Loss Of Cell Delineation (LCD) - This read only bit indicate that a Loss of Cell Delineation state exists. LCD occurs when OCD persists for the period programmed in the LCD threshold control register RLTC.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RECL 0 6 RCHL 0
RCPSRL1 Receive Cell Processor Status Register Latched 1 1010, 1210, 1410, 1610
5 RIDL 0
4 RUDL 0
3 RIVDL 0
2 RECCL 0
1 RHPCL 0
0 RCHCL 0
Bit 7 : Receive Errored Header Cell Latched (RECL) - This bit is set when a cell with an errored header is discarded. Bit 6 : Receive Corrected Header Cell Latched (RCHL) - This bit is set when a cell with a single header error is corrected. Bit 5 : Receive Idle Cell Detection Latched (RIDL) - This bit is set when an idle cell is discarded. Bit 4 : Receive Unassigned Cell Detection Latched (RUDL) - This bit is set when an unassigned cell is discarded. Bit 3 : Receive Invalid Cell Detection Latched (RIVDL) - This bit is set when an invalid cell is discarded. Bit 2 : Receive Errored Header Cell Count Latched (RECCL) - This bit is set when the RECC bit in the RCPSR register transitions from zero to one. Bit 1 : Receive Header Pattern Cell Count Latched (RHPCL) - This bit is set when the RHPC bit in the RCPSR register transitions from zero to one. Bit 0 : Receive Corrected Header Cell Count Latched (RCHCL) - This bit is set when the RCHC bit in the RCPSR register transitions from zero to one.
Register Name: Register Description: Address (hex): Bit # Name Default 7 SPRL 0 6 -0
RCPSRL2 Receive Cell Processor Status Register Latched 2 1011, 1211, 1411, 1611
5 -0
4 -0
3 OOSL 0
2 COCDL 0
1 OCDCL 0
0 LCDCL 0
Bit 7 : Spare Change Latched (SPRL) - This bit is set when the SPR bit changes state. Bits 6 to 4 : Unused Bit 3 : Out Of Sync Change Latched (OOSL) - This bit is set when the OOS bit in the RCPSR2 register changes state. Bit 2 : Change Of Cell Delineation Latched (COCDL) - This bit is set when the data path cell counters are updated with a new cell delineation that is different from the previous cell delineation. Bit 1 : Out Of Cell Delineation Change Latched (OCDCL) - This bit is set when the OCD bit in the RCPSR2 register changes state. Note: Immediately after a reset, this bit will be set to one. Bit 0 : Loss Of Cell Delineation Change Latched (LCDCL) - This bit is set when the LCD bit in the RCPSR2 register changes state
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 RECIE 0 6 RCHIE 0
RCPSRIE Receive Cell Processor Register Interrupt Enable 1012, 1212, 1412, 1612
5 RIDIE 0
4 RUDIE 0
3 RIVDIE 0
2 RECCIE 0
1 RHPCIE 0
0 RCHCIE 0
Bit 7 : Receive Errored Header Cell Interrupt Enable (RECIE) - This bit enables an interrupt if the RECL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 6 : Receive Corrected Header Cell Interrupt Enable (RCHIE) - This bit enables an interrupt if the RCHL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 5 : Receive Idle Cell Detection Interrupt Enable (RIDIE) - This bit enables an interrupt if the RIDL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 4 : Receive Unassigned Cell Detection Interrupt Enable (RUDIE) - This bit enables an interrupt if the RUDL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 3 : Receive Invalid Cell Detection Interrupt Enable (RIVDIE) - This bit enables an interrupt if the RIVDL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 2 : Receive Errored Header Cell Count Interrupt Enable (RECCIE) - This bit enables an interrupt if the RECCL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 1 : Receive Header Pattern Cell Count Interrupt Enable (RHPCIE) - This bit enables an interrupt if the RHFCL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 0 : Receive Corrected Header Cell Count Interrupt Enable (RCHCIE) - This bit enables an interrupt if the RCHCL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 SPRIE 0 6 -0
RCPSRIE Receive Cell Processor Register Interrupt Enable 1013, 1213, 1413, 1613
5 -0
4 -0
3 OOSIE 0
2 COCDIE 0
1 OCDCIE 0
0 LCDCIE 0
Bit 7 : Spare Change Interrupt Enable (SPRIE) - This bit enables an interrupt if the SPRL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bits 6 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Out Of Sync Change Interrupt Enable (OOSIE) - This bit enables an interrupt if the OOSL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 2 : Change Of Cell Delineation Interrupt Enable (COCDIE) - This bit enables an interrupt if the COCDL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 1 : Out Of Cell Delineation Change Interrupt Enable (OCDCIE) - This bit enables an interrupt if the OCDCL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 0 : Loss Of Cell Delineation Change Interrupt Enable (LCDCIE) - This bit enables an interrupt if the LCDCL bit in the RCPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Cell Count (RCC[23:0]) - These twenty-four bits indicate the number of cells stored in the receive FIFO. Note: Cells discarded due to system loopback or an overflow condition will be included in this count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RCC7 0 6 RCC6 0
RCCR1 Receive Cell Count Register 1 1014, 1214, 1414, 1614
5 RCC5 0
4 RCC4 0
3 RCC3 0
2 RCC2 0
1 RCC1 0
0 RCC0 0
Bits 7 to 0 : Receive Cell Count (RCC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 15 RCC15 0 14 RCC14 0
RCCR2 Receive Cell Count Register 2 1015, 1215, 1415, 1615
13 RCC13 0
12 RCC12 0
11 RCC11 0
10 RCC10 0
9 RCC9 0
8 RCC8 0
Bits 7 to 0 : Receive Cell Count (RCC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RCC23 0 6 RCC22 0
RCCR3 Receive Cell Count Register 3 1016, 1216, 1416, 1616
5 RCC21 0
4 RCC20 0
3 RCC19 0
2 RCC18 0
1 RCC17 0
0 RCC16 0
Bits 7 to 0 : Receive Cell Count (RCC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Errored Header Count (RECC[23:0]) - These twenty-four bits indicate the number of cells received with uncorrected header errors and discarded. If errored cell extraction is disabled, this count will be zero. Cells included in this count will not be included in any other count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RECC7 0 6 RECC6 0
REHCR1 Receive Errored Header Count Register 1 1018, 1218, 1418, 1618
5 RECC5 0
4 RECC4 0
3 RECC3 0
2 RECC2 0
1 RECC1 0
0 RECC0 0
Bits 7 to 0 : Receive Errored Header Count (RECC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RECC15 0
REHCR2 Receive Errored Header Count Register 2 1019, 1219, 1419, 1619
6 RECC14 0
5 RECC13 0
4 RECC12 0
3 RECC11 0
2 RECC10 0
1 RECC9 0
0 RECC8 0
Bits 7 to 0 : Receive Errored Header Count (RECC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RECC23 0
REHCR3 Receive Errored Header Count Register 3 101A, 121A, 141A, 161A
6 RECC22 0
5 RECC21 0
4 RECC20 0
3 RECC19 0
2 RECC18 0
1 RECC17 0
0 RECC16 0
Bits 7 to 0 : Receive Errored Header Count (RECC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Header Pattern Comparison Cell Count (RHPC[23:0]) - These twenty-four bits indicate the number of cells identified during the header pattern comparison processes. In the header pattern comparison count and discard match modes, this will be a count of cells with a matching header. In the header pattern comparison count and discard no match modes, this will be a count of cells without a matching header. In the header pattern comparison count (match or no match) modes, this count will also be included in the receive cell count register (RCCR). In the header pattern comparison discard (match or no match) modes, this count will not be included in any other count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHPC7 0 6 RHPC6 0
RHPCR1 Receive Header Pattern Cell Count Register #1 101C, 121C, 141C, 161C
5 RHPC5 0
4 RHPC4 0
3 RHPC3 0
2 RHPC2 0
1 RHPC1 0
0 RHPC0 0
Bits 7 to 0 : Receive Header Pattern Comparison Cell Count (RHPC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHPC15 0
RHPCR2 Receive Header Pattern Cell Count Register 2 101D, 121D, 141D, 161D
6 RHPC14 0
5 RHPC13 0
4 RHPC12 0
3 RHPC11 0
2 RHPC10 0
1 RHPC9 0
0 RHPC8 0
Bits 7 to 0 : Receive Header Pattern Comparison Cell Count (RHPC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHPC23 0
RHPCR3 Receive Header Pattern Cell Count Register 3 101E, 121E, 141E, 161E
6 RHPC22 0
5 RHPC21 0
4 RHPC20 0
3 RHPC19 0
2 RHPC18 0
1 RHPC17 0
0 RHPC16 0
Bits 7 to 0 : Receive Header Pattern Comparison Cell Count (RHPC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Corrected Header Count (RCHC[23:0]) - These twenty-four bits indicate the number of cells that have had header errors corrected. If header error correction is disabled, this count will be zero. This count will be included in the receive cell count register (RCCR), receive filtered idle/unassigned/invalid cell count register (RFCCR), or receive header pattern cell count register (RHPCR).
Register Name: Register Description: Address (hex): Bit # Name Default 7 RCHC7 0 6 RCHC6 0
RCCCR1 Receive Corrected Cell Count Register #1 1020, 1220, 1420, 1620
5 RCHC5 0
4 RCHC4 0
3 RCHC3 0
2 RCHC2 0
1 RCHC1 0
0 RCHC0 0
Bits 7 to 0 : Receive Corrected Header Count (RCHC[15:0])
Register Name: Register Description: Address (hex): Bit # Name Default 15 RCHC15 0
RCCCR2 Receive Corrected Cell Count Register 2 1021, 1221, 1421, 1621
14 RCHC14 0
13 RCHC13 0
12 RCHC12 0
11 RCHC11 0
10 RCHC10 0
9 RCHC9 0
8 RCHC8 0
Bits 7 to 0 : Receive Corrected Header Count (RCHC[15:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RCHC23 0
RCCCR3 Receive Corrected Cell Count Register 3 1022, 1222, 1422, 1622
6 RCHC22 0
5 RCHC21 0
4 RCHC20 0
3 RCHC19 0
2 RCHC18 0
1 RCHC17 0
0 RCHC16 0
Bits 7 to 0 : Receive Corrected Header Count (RCHC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Filtered Cell Count (RFCC[23:0]) - These twenty-four bits indicate the number of cells that were discarded during the cell filtering processes (idle, unassigned, and/or invalid). If all cell filtering is disabled, this count will be zero. Cells included in this count will not be included in any other count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFCC7 0 6 RFCC6 0
RFCCR1 Receive Filtered Idle/Unassigned/Invalid Cell Count Register 1 1024, 1224, 1424, 1624
5 RFCC5 0
4 RFCC4 0
3 RFCC3 0
2 RFCC2 0
1 RFCC1 0
0 RFCC0 0
Bits 7 to 0 : Receive Filtered Cell Count (RFCC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFCC15 0
RFCCR2 Receive Filtered Idle/Unassigned/Invalid Cell Count Register 2 1025, 1225, 1425, 1625
6 RFCC14 0
5 RFCC13 0
4 RFCC12 0
3 RFCC11 0
2 RFCC10 0
1 RFCC9 0
0 RFCC8 0
Bits 7 to 0 : Receive Filtered Cell Count (RFCC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFCC23 0
RFCCR3 Receive Filtered Idle/Unassigned/Invalid Cell Count Register 3 1026, 1226, 1426, 1626
6 RFCC22 0
5 RFCC21 0
4 RFCC20 0
3 RFCC19 0
2 RFCC18 0
1 RFCC17 0
0 RFCC16 0
Bits 7 to 0 : Receive Filtered Cell Count (RFCC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.7 Receive Packet Processor Registers
Table 11-6 Receive Packet Processor Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1000 1001 1002 1003 1004 - 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C 101D 101E 101F 1020 1021 1022 1023 - 1027 1028 1029 102A 102B 102C 102D 102E 102F 1030 - 103F
NAME
FUNCTION
RPPC1 RPPC2 RMPSC1 RMPSC2 RPPSR RPPSRL RPPSRIE RPCR1 RPCR2 RPCR3 RFPCR1 RFPCR2 RFPCR3 RAPCR1 RAPCR2 RAPCR3 RSPCR1 RSPCR2 RSPCR3 RBCR1 RBCR2 RBCR3 RBCR4 RABCR1 RABCR2 RABCR3 RABCR4 --
Receive Packet Processor Control Register 1 Receive Packet Processor Control Register 2 Receive Maximum Packet Size Control Register 1 Receive Maximum Packet Size Control Register 2 Unused. Must be set = 0 for proper operation. Receive Packet Processor Status Register Unused. Must be set = 0 for proper operation. Receive Packet Processor Status Register Latched Unused. Must be set = 0 for proper operation. Receive Packet Processor Status Register Interrupt Enable Receive Packet Count Register 1 Receive Packet Count Register 2 Receive Packet Count Register 3 Unused. Must be set = 0 for proper operation. Receive FCS Errored Packet Count Register 1 Receive FCS Errored Packet Count Register 2 Receive FCS Errored Packet Count Register 3 Unused. Must be set = 0 for proper operation. Receive Aborted Packet Count Register 1 Receive Aborted Packet Count Register 2 Receive Aborted Packet Count Register 3 Unused. Must be set = 0 for proper operation. Receive Size Violation Packet Count Register 1 Receive Size Violation Packet Count Register 2 Receive Size Violation Packet Count Register 3 Unused. Must be set = 0 for proper operation. Receive Byte Count Register 1 Receive Byte Count Register 2 Receive Byte Count Register 3 Receive Byte Count Register 4 Receive Aborted Byte Count Register 1 Receive Aborted Byte Count Register 2 Receive Aborted Byte Count Register 3 Receive Aborted Byte Count Register 4 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 SPARE 0 6 0
RPPC1 Receive Packet Processor Control Register 1 1000, 1200, 1400, 1600
5 RFPD 0
4 RF16 0
3 RFED 0
2 RDD 0
1 RBRE 0
0 RCCE 0
Bit 7 : Spare Configuration Bit (SPARE) - This bit is a spare configuration bit reserved for future use. It can be written to and read from, however it does not effect the operation of the CELL / PACKET INTERFACE. Bit 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Receive FCS Processing Disable (RFPD) - When 0, FCS processing is performed (the packets have an FCS appended). When 1, FCS processing is disabled (the packets do not have an FCS appended). Bit 4 : Receive FCS-16 Enable (RF16) - When 0, the error checking circuit uses a 32-bit FCS. When 1, the error checking circuit uses a 16-bit FCS. This bit is ignored when FCS processing is disabled. Bit 3 : Receive FCS Extraction Disable (RFED) - When 0, the FCS bytes are discarded. When 1, the FCS bytes are passed on. This bit is ignored when FCS processing is disabled. Bit 2 : Receive Descrambling Disable (RDD) - When 0, descrambling is performed. When 1, descrambling is disabled. Bit 1 : Receive Bit Reordering Enable (RBRE) - When 0, bit reordering is disabled (The first bit received is stored in the MSB of the receive FIFO byte RFD[7]). When 1, bit reordering is enabled (The first bit received is stored in the LSB of the receive FIFO byte RFD[0]). Bit 0 : Receive Clear Channel Enable (RCCE) - When 0, packet processing is enabled. When 1, clear channel is enabled, and all packet-processing functions except descrambling and bit reordering are disabled.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RMNS7 0 6 RMNS6 0
RPPC2 Receive Packet Processor Control Register 2 1001, 1201, 1401, 1601
5 RMNS5 0
4 RMNS4 0
3 RMNS3 0
2 RMNS2 0
1 RMNS1 0
0 RMNS0 0
Bits 7 to 0 : Receive Minimum Packet Size (RMNS[7:0]) - These eight bits indicate the minimum allowable packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: In FCS-32 mode, packets with six bytes are the minimum packet size allowed. In FCS-16 mode, packets with four bytes are the minimum packet size allowed. When FCS processing is disabled, packets with two bytes are the minimum packet size allowed.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 RMX7 0 6 RMX6 0
RMPSC1 Receive Maximum Packet Size Control Register 1 1002, 1202, 1402, 1602
5 RMX5 0
4 RMX4 0
3 RMX3 0
2 RMX2 0
1 RMX1 0
0 RMX0 0
Bits 7 to 0 : Receive Maximum Packet Size (RMX[7:0]) - These sixteen bits indicate the maximum allowable packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: If the maximum packet length is less than the minimum packet length, all packets will be discarded. When packet processing is disabled, these sixteen bits indicate the "packet" size the incoming data is to be broken into.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RMX15 0 6 RMX14 0
RMPSC2 Receive Maximum Packet Size Control Register 2 1003, 1203, 1403, 1603
5 RMX13 0
4 RMX12 0
3 RMX11 0
2 RMX10 1
1 RMX9 1
0 RMX8 0
Bits 7 to 0 : Receive Maximum Packet Size (RMX[15:8]) - These sixteen bits indicate the maximum allowable packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: If the maximum packet length is less than the minimum packet length, all packets will be discarded. When packet processing is disabled, these sixteen bits indicate the "packet" size the incoming data is to be broken into.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RPPSR Receive Packet Processor Status Register 100F, 120F, 140F, 160F
5 -0
4 -0
3 -0
2 REPC 0
1 RAPC 0
0 RSPC 0
Bits 7 to 3 : Unused. Bit 2 : Receive FCS Errored Packet Count (REPC) - This read only bit indicates that the receive FCS errored packet count is non-zero. Bit 1 : Receive Aborted Packet Count (RAPC) - This read only bit indicates that the receive aborted packet count is non-zero. Bit 0 : Receive Size Violation Packet Count (RSPC) - This read only bit indicates that the receive size violation packet count is non-zero.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 REPL 0 6 RAPL 0
RPPSRL Receive Packet Processor Status Register Latched 1011, 1211, 1411, 1611
5 RIPDL 0
4 RSPDL 0
3 RLPDL 0
2 REPCL 0
1 RAPCL 0
0 RSPCL 0
Bit 7 : Receive FCS Errored Packet Latched (REPL) - This bit is set when a packet with an errored FCS is detected. Bit 6 : Receive Aborted Packet Latched (RAPL) - This bit is set when a packet with an abort indication is detected. Bit 5 : Receive Invalid Packet Detected Latched (RIPDL) - This bit is set when a packet with a non-integer number of bytes is detected. Bit 4 : Receive Small Packet Detected Latched (RSPDL) - This bit is set when a packet smaller than the minimum packet size is detected. Bit 3 : Receive Large Packet Detected Latched (RLPDL) - This bit is set when a packet larger than the maximum packet size is detected. Bit 2 : Receive FCS Errored Packet Count Latched (REPCL) - This bit is set when the REPC bit in the RPPSR register transitions from zero to one. Bit 1 : Receive Aborted Packet Count Latched (RAPCL) - This bit is set when the RAPC bit in the RPPSR register transitions from zero to one. Bit 0 : Receive Size Violation Packet Count Latched (RSPCL) - This bit is set when the RSPC bit in the RPPSR register transitions from zero to one.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 REPIE 0 6 RAPIE 0
RPPSRIE Receive Packet Processor Status Register Interrupt Enable 1013, 1213, 1413, 1613
5 RIPDIE 0
4 RSPDIE 0
3 RLPDIE 0
2 REPCIE 0
1 RAPCIE 0
0 RSPCIE 0
Bit 7 : Receive FCS Errored Packet Interrupt Enable (REPIE) - This bit enables an interrupt if the REPL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 6 : Receive Aborted Packet Interrupt Enable (RAPIE) - This bit enables an interrupt if the RAPL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 5 : Receive Invalid Packet Detected Interrupt Enable (RIPDIE) - This bit enables an interrupt if the RIPDL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 4 : Receive Small Packet Detected Interrupt Enable (RSPDIE) - This bit enables an interrupt if the RSPDL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 3 : Receive Large Packet Detected Interrupt Enable (RLPDIE) - This bit enables an interrupt if the RLPDL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 2 : Receive FCS Errored Packet Count Interrupt Enable (REPCIE) - This bit enables an interrupt if the REPCL bit in the RPPSRL register is set. Must be set low when the packets do not have an FCS appended. 0 = interrupt disabled 1 = interrupt enabled Bit 1 : Receive Aborted Packet Count Interrupt Enable (RAPCIE) - This bit enables an interrupt if the RAPCL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 0 : Receive Size Violation Packet Count Interrupt Enable (RSPCIE) - This bit enables an interrupt if the RSPCL bit in the RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Packet Count (RPC[23:0]) - These twenty-four bits indicate the number of packets stored in the receive FIFO without an abort indication. Note: Packets discarded due to system loopback or an overflow condition will be included in this count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RPC7 0 6 RPC6 0
RPCR1 Receive Packet Count Register 1 1014, 1214, 1414, 1614
5 RPC5 0
4 RPC4 0
3 RPC3 0
2 RPC2 0
1 RPC1 0
0 RPC0 0
Bits 7 to 0 : Receive Packet Count (RPC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RPC15 0 6 RPC14 0
RPCR2 Receive Packet Count Register 2 1015, 1215, 1415, 1615
5 RPC13 0
4 RPC12 0
3 RPC11 0
2 RPC10 0
1 RPC9 0
0 RPC8 0
Bits 7 to 0 : Receive Packet Count (RPC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RPC23 0 6 RPC22 0
RPCR3 Receive Packet Count Register 3 1016, 1216, 1416, 1616
5 RPC21 0
4 RPC20 0
3 RPC19 0
2 RPC18 0
1 RPC17 0
0 RPC16 0
Bits 7 to 0 : Receive Packet Count (RPC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive FCS Errored Packet Count (RFPC[23:0]) - These twenty-four bits indicate the number of packets received with an FCS error. The byte count for these packets is included in the receive aborted byte count register REBCR.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFPC7 0 6 RFPC6 0
RFPCR1 Receive FCS Errored Packet Count Register 1 1018, 1218, 1418, 1618
5 RFPC5 0
4 RFPC4 0
3 RFPC3 0
2 RFPC2 0
1 RFPC1 0
0 RFPC0 0
Bits 7 to 0 : Receive FCS Errored Packet Count (RFPC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFPC15 0
RFPCR2 Receive FCS Errored Packet Count Register 2 1019, 1219, 1419, 1619
6 RFPC14 0
5 RFPC13 0
4 RFPC12 0
3 RFPC11 0
2 RFPC10 0
1 RFPC9 0
0 RFPC8 0
Bits 7 to 0 : Receive FCS Errored Packet Count (RFPC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFPC23 0
RFPCR3 Receive FCS Errored Packet Count Register 3 1020, 1220, 1420, 1620
6 RFPC22 0
5 RFPC21 0
4 RFPC20 0
3 RFPC19 0
2 RFPC18 0
1 RFPC17 0
0 RFPC16 0
Bits 7 to 0 : Receive FCS Errored Packet Count (RFPC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Aborted Packet Count (RAPC[23:0]) - These twenty-four bits indicate the number of packets received with a packet abort indication. The byte count for these packets is included in the receive aborted byte count register REBCR.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RAPC7 0 6 RAPC6 0
RAPCR1 Receive Aborted Packet Count Register 1 101C, 121C, 141C, 161C
5 RAPC5 0
4 RAPC4 0
3 RAPC3 0
2 RAPC2 0
1 RAPC1 0
0 RAPC0 0
Bits 7 to 0 : Receive Aborted Packet Count (RAPC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RAPC15 0
RAPCR2 Receive Aborted Packet Count Register 2 101D, 121D, 141D, 161D
6 RAPC14 0
5 RAPC13 0
4 RAPC12 0
3 RAPC11 0
2 RAPC10 0
1 RAPC9 0
0 RAPC8 0
Bits 7 to 0 : Receive Aborted Packet Count (RAPC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RAPC23 0
RAPCR3 Receive Aborted Packet Count Register 3 101E, 121E, 141E, 161E
6 RAPC22 0
5 RAPC21 0
4 RAPC20 0
3 RAPC19 0
2 RAPC18 0
1 RAPC17 0
0 RAPC16 0
Bits 7 to 0 : Receive Aborted Packet Count (RAPC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Size Violation Packet Count (RSPC[23:0]) - These twenty-four bits indicate the number of packets received with a packet size violation (below minimum, above maximum, or non-integer number of bytes). The byte count for these packets is included in the receive aborted byte count register REBCR.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RSPC7 0 6 RSPC6 0
RSPCR1 Receive Size Violation Packet Count Register 1 1020, 1220, 1420, 1620
5 RSPC5 0
4 RSPC4 0
3 RSPC3 0
2 RSPC2 0
1 RSPC1 0
0 RSPC0 0
Bits 7 to 0 : Receive Size Violation Packet Count (RSPC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RSPC15 0
RSPCR2 Receive Size Violation Packet Count Register 2 1021, 1221, 1421, 1621
6 RSPC14 0
5 RSPC13 0
4 RSPC12 0
3 RSPC11 0
2 RSPC10 0
1 RSPC9 0
0 RSPC8 0
Bits 7 to 0 : Receive Size Violation Packet Count (RSPC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RSPC23 0
RSPCR3 Receive Size Violation Packet Count Register 3 1022, 1222, 1422, 1622
6 RSPC22 0
5 RSPC21 0
4 RSPC20 0
3 RSPC19 0
2 RSPC18 0
1 RSPC17 0
0 RSPC16 0
Bits 7 to 0 : Receive Size Violation Packet Count (RSPC[23:16])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Byte Count (RBC[31:0]) - These thirty-two bits indicate the number of bytes contained in packets stored in the receive FIFO without an abort indication. Note: Bytes discarded due to FCS extraction, system loopback, FIFO reset, or an overflow condition may be included in this count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RBC7 0 6 RBC6 0
RBCR1 Receive Byte Count Register 1 1028, 1228, 1428, 1628
5 RBC5 0
4 RBC4 0
3 RBC3 0
2 RBC2 0
1 RBC1 0
0 RBC0 0
Bits 7 to 0 : Receive Byte Count (RBC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RBC15 0 6 RBC14 0
RBCR2 Receive Byte Count Register 2 1029, 1229, 1429, 1629
5 RBC13 0
4 RBC12 0
3 RBC11 0
2 RBC10 0
1 RBC9 0
0 RBC8 0
Bits 7 to 0 : Receive Byte Count (RBC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RBC23 0 6 RBC22 0
RBCR3 Receive Byte Count Register 3 102A, 122A, 142A, 162A
5 RBC21 0
4 RBC20 0
3 RBC19 0
2 RBC18 0
1 RBC17 0
0 RBC16 0
Bits 7 to 0 : Receive Byte Count (RBC[23:16])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RBC31 0 6 RBC30 0
RBCR4 Receive Byte Count Register 4 102B, 122B, 142B, 162B
5 RBC29 0
4 RBC28 0
3 RBC27 0
2 RBC26 0
1 RBC25 0
0 RBC24 0
Bits 7 to 0 : Receive Byte Count (RBC[31:24])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Receive Aborted Byte Count (RABC[31:0]) - These thirty-two bits indicate the number of bytes contained in packets stored in the receive FIFO with an abort indication. Note: Bytes discarded due to FCS extraction, system loopback, FIFO reset, or an overflow condition may be included in this count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RABC7 0 6 RABC6 0
RABCR1 Receive Aborted Byte Count Register 1 102C, 122C, 142C, 162C
5 RABC5 0
4 RABC4 0
3 RABC3 0
2 RABC2 0
1 RABC1 0
0 RABC0 0
Bits 7 to 0 : Receive Aborted Byte Count (RABC[7:0])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RABC15 0
RABCR2 Receive Aborted Byte Count Register 2 102D, 122D, 142D, 162D
6 RABC14 0
5 RABC13 0
4 RABC12 0
3 RABC11 0
2 RABC10 0
1 RABC9 0
0 RABC8 0
Bits 7 to 0 : Receive Aborted Byte Count (RABC[15:8])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RABC23 0
RABCR3 Receive Aborted Byte Count Register 3 102E, 122E, 142E, 162E
6 RABC22 0
5 RABC21 0
4 RABC20 0
3 RABC19 0
2 RABC18 0
1 RABC17 0
0 RABC16 0
Bits 7 to 0 : Receive Aborted Byte Count (RABC[23:16])
Register Name: Register Description: Address (hex): Bit # Name Default 7 RABC31 0
RABCR4 Receive Aborted Byte Count Register 4 102F, 122F, 142F, 162F
6 RABC30 0
5 RABC29 0
4 RABC28 0
3 RABC27 0
2 RABC26 0
1 RABC25 0
0 RABC24 0
Bits 7 to 0 : Receive Aborted Byte Count (RABC[31:24])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2.8 Receive FIFO Registers
Table 11-7 Receive FIFO Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 108A 108B-108F
NAME
FUNCTION
RFC RFLC1 RFLC2 RFPAC RFSRL RFSRIE -
Receive FIFO Control Register Unused. Must be set = 0 for proper operation. Receive FIFO Level Control Register 1 Receive FIFO Level Control Register 2 Receive FIFO Port Address Control Register Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Receive FIFO Status Register Latched Unused. Must be set = 0 for proper operation. Receive FIFO Status Register Interrupt Enable Unused. Must be set = 0 for proper operation.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RFC Receive FIFO Control Register 1080, 1280, 1480, 1680
5 -0
4 -0
3 -0
2 -0
1 -0
0 RFRST 1
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Receive FIFO Reset (RFRST) - When 0, the Receive FIFO will resume normal operations, however, data is discarded until a start of packet/cell is received after RAM power-up is completed. When 1, the Receive FIFO is emptied, any transfer in progress is halted, the FIFO RAM is powered down, the associated RDXA signal is forced low, and all incoming data is discarded. If the port was selected when the reset was initiated, the port will be deselected, and must be reselected (REN deasserted with address on RADR or RSX asserted with address on RDAT) before any transfer will occur.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 0 6 0
RFLC1 Receive FIFO Level Control Register 1 1082, 1282, 1482, 1682
5 RFAF5 0
4 RFAF4 1
3 RFAF3 0
2 RFAF2 0
1 RFAF1 0
0 RFAF0 0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation. Bits 5 to 0 : Receive FIFO Almost Full Level (RFAF[5:0]) - In POS-PHY packet processing mode, these six bits indicate the maximum number of four byte groups that can be available in the Receive FIFO for it to be considered "almost full". E.g., a value of 30 (1Eh) results in the FIFO being "almost full" when it has 120 (78h) bytes or less available. In cell processing mode, these bits are ignored.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RFLC2 Receive FIFO Level Control Register 2 1083, 1283, 1483, 1683
5 RFAE5 0
4 RFAE4 1
3 RFAE3 0
2 RFAE2 0
1 RFAE1 0
0 RFAE0 0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation. Bits 5 to 0 : Receive FIFO Almost Empty Level (RFAE[5:0]) - In POS-PHY packet processing mode, these six bits indicate the maximum number of four byte groups that can be stored in the Receive FIFO for it to be considered "almost empty". E.g., a value of 30 (1Eh) results in the FIFO being "almost empty" when it contains 120 (78h) bytes or less. In cell processing mode, RFAE[5:2] are ignored, and RFAE[1:0] indicate the maximum number of cells that can be stored in the Receive FIFO for it to be considered "almost empty".
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 RPA7 0 6 RPA6 0
RFPAC Receive FIFO Port Address Control Register 1084, 1284, 1484, 1684
5 RPA5 0
4 RPA4 0
3 RPA3 0
2 RPA2 0
1 RPA1 0
0 RPA0 0
Bits 7 to 0 : Receive FIFO System Port Address (RPA[7:0]) - These eight bits set the Receive FIFO system interface port address used to poll the Receive FIFO for fill status, and select it for data transfer. Each port in the device must have a different port address. In Level II mode, bits RPA[7:5] are ignored, and if bits RPA[4:0] are set to a value of 1Fh, the port is disabled.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RFSRL Receive FIFO Status Register Latched 1088, 1288, 1488, 1688
5 -0
4 -0
3 -0
2 -0
1 -0
0 RFOL 0
Bits 7 to 1 : Unused Bit 0 : Receive FIFO Overflow Latched (RFOL) - This bit is cleared when a logic one is written to this bit, and set when a Receive FIFO overflow condition occurs. An overflow condition results in a loss of data.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RFSRIE Receive FIFO Status Register Interrupt Enable 108A, 128A, 148A, 168A
5 -0
4 -0
3 -0
2 -0
1 -0
0 RFOIE 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Receive FIFO Overflow Interrupt Enable (RFOIE) - This bit enables an interrupt if the RFOL bit in the RFSRL register is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.3 System Interface Registers
11.3.1 Transmit System Interface Registers
Table 11-8 Transmit System Interface Register Map
ADDRESS (hex) 1940 1941 1942 1943 1944 1945 - 194F NAME TSIC1 TSIC2 TSISRL TSISRIE FUNCTION Transmit System Interface Control Register 1 Transmit System Interface Control Register 2 Transmit System Interface Status Register Latched Unused. Must be set = 0 for proper operation. Transmit System Interface Status Register Interrupt Enable Unused. Must be set = 0 for proper operation.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TSIC1 Transmit System Interface Control Register 1 1940
5 -0
4 -0
3 TPARP 0
2 TFLVI 0
1 TSBRE 0
0 THECT 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Transmit System Parity Polarity (TPARP) - When 0, the TPAR signal will maintain odd parity (for all 0''s, TPAR is high). When 1, the TPAR signal will maintain even parity (for all 0''s, TPAR is low). Bit 2 : Transmit System Fill Level Inversion (TFLVI) - When 0, the polarity of the TPXA, TDXA, and TSPA signals will be normal (high for data available). When 1, the polarity of the TPXA, TDXA, and TSPA signals will be inverted (low for data available). Bit 1 : Transmit System Interface Byte Reordering Enable (TSBRE) - When 0, byte reordering is disabled, and the first byte transmitted is transferred across the system interface as the most significant byte (TDAT[15:8] in 16-bit mode). When 1, byte reordering is enabled, and the first byte transmitted is transferred across the system interface as the least significant byte (TDAT[7:0]). Bit 0 : Transmit System HEC Transfer (THECT) - When 0, The HEC byte is not transferred across the transmit system interface. When 1, the HEC byte is transferred across the transmit system interface with the cell data.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TSIC2 Transmit System Interface Control Register 2 1941
5 TXAD5 0
4 TXAD4 0
3 TXAD3 0
2 TXAD2 0
1 TXAD1 0
0 TXAD0 0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation. Bits 5 to 0 : Transmit Cell/Packet Available Deassertion Time (TXAD[5:0]) - These six bits indicate the amount of data that can be transferred after the cell/packet available signal is deasserted. If more than the indicated amount of data is transferred, a Transmit FIFO overflow may occur.
In UTOPIA mode, only TXAD[2:0] are valid, and they indicate the number of transfers before the Transmit FIFO is full. For UTOPIA Level 2, a value of 00h enables the default mode, which is 5. (TDXA will transition low on the edge that samples payload byte 43 in 8-bit mode, payload bytes 37 and 38 in 16-bit mode.) For UTOPIA Level 3, a value of 00h or 01h enables the default mode. The default for UTOPIA Level 3 is for TDXA to transition low on the clock edge following the edge that samples the start of a cell. In POS-PHY mode, TXAD[5:0] indicate the number of 4-byte data groups that can be written into the Transmit FIFO before it is full (maximum value 56 or 38h). In POS-PHY Level 2, a value of 00h enables the default mode, which is 1. (For an x-byte transfer, TDXA and TSPA will transition low on the edge that samples byte x-4 in 8-bit mode, bytes x-5 and x-4 in 16-bit mode.) In POS-PHY Level 3 (8-bit), a value of 00h enables the default mode, which is 1. (For an x-byte transfer, TDXA and TSPA will transition low on the edge that samples byte x-4). For POS-PHY Level 3 (16-bit), a value of 00h or 01h enables the default mode, which is 2. (For an x-byte transfer, TDXA and TSPA will transition low on the edge that samples bytes x-9 and x-8.) Note: A packet that is 4x+1, 4x+2, 4x+3, or 4x+4 (where x is an integer) bytes long consumes x+1 four byte data groups of space in the FIFO. This includes 2-byte and 3byte packets, which consume a 4-byte data group of space in the FIFO.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TSISRL Transmit System Interface Status Register Latched 1942
5 -0
4 -0
3 -0
2 -0
1 TCLKAL 0
0 TPREL 0
Bits 7 to 2 : Unused. Bit 1 : Transmit System Interface Clock Active (TCLKAL) - This bit is set when TSCLK samples the associated transmit system interface inputs. Bit 0 : Transmit System Interface Parity Error Latched (TPREL) - This bit is set when a parity error is detected during a data transfer on the Transmit System Interface bus.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
TSISRIE Transmit System Interface Status Register Interrupt Enable 1944
5 -0
4 -0
3 -0
2 -0
1 -0
0 TPREIE 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Transmit System Interface Parity Error Interrupt Enable (TPREIE) - This bit enables an interrupt if the TPREL bit in the TSISRL register is set. 0 = interrupt disabled 1 = interrupt enabled
11.3.2 Receive System Interface Registers
Table 11-9 Receive System Interface Register Map
Address (hex) 1900 1901 1902 1903 1904 1905-190F NAME RSIC1 RSIC2 RSIC3 RSIC4 RSISRL FUNCTION Receive System Interface Control Register 1 Receive System Interface Control Register 2 Receive System Interface Control Register 3 Receive System Interface Control Register 4 Receive System Interface Status Register Latched Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.3.2.1 Register Bit Descriptions
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 RXAD2 0
RSIC1 Receive System Interface Control Register 1 1900
5 RXAD1 0
4 RXAD0 0
3 RPARP 0
2 RFLVI 0
1 RSBRE 0
0 RHECT 0
Bit 7 : Unused. Must be set = 0 for proper operation. Bits 6 to 4 : Receive Cell Available Deassertion Time (RXAD[2:0]) - These three bits indicate the number of transfers that will occur after the selected Receive FIFO indicates it is "empty". A value of 000, enables the default mode. The default for UTOPIA Level 2 is 0 (RDXA will transition low on the clock edge following the clock edge that outputs payload byte 48 in 8-bit mode, payload bytes 47 and 48 in 16-bit mode). The default for UTOPIA Level 3 is for RDXA to transition low on the clock edge that outputs the start of cell. These bits are ignored in POS-PHY mode. Bit 3 : Receive System Parity Polarity (RPARP) - When 0, the RPAR signal will maintain odd parity (for all 0''s, RPAR is high). When 1, the RPAR signal will maintain even parity (for all 0''s, RPAR is low). Bit 2 : Receive System Fill Level Inversion (RFLVI) - When 0, the polarity of the RPXA and RDXA signals will be normal (high for data available). When 1, the polarity of the RPXA and RDXA signals will be inverted (low for data available). Bit 1 : Receive System Interface Byte Reordering Enable (RSBRE) - When 0, byte reordering is disabled, and the first byte received is transferred across the system interface as the most significant byte (RDAT[15:8] in 16-bit mode). When 1, byte reordering is enabled, and the first byte received is transferred across the system interface as the least significant byte (RDAT[7:0]). Bit 0 : Receive System HEC Transfer Enable (RHECT) - When 0, The HEC byte is not transferred across the receive system interface. When 1, the HEC byte is transferred across the receive system interface with the cell data.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RSIC2 Receive System Interface Control Register 2 1901
5 -0
4 -0
3 -0
2 RMDT2 0
1 RMDT1 0
0 RMDT0 0
Bits 7 to 3 : Unused. Must be set = 0 for proper operation. Bit 2 to 0 : Receive System RVAL Minimum Deassertion Time (RMDT[2:0]) - These three bits indicate the minimum number of clock cycles that RVAL must remain deasserted between packets transferred from the same port, a transfer of data equal to the maximum burst length (if enabled), or before RSX can be asserted. A value of zero, means that RVAL will not deassert between packets transferred from the same port or between transfers of the maximum burst length when no other port has data available. These bits are ignored in UTOPIA and POS-PHY Level II modes. Note: The RVAL minimum deassertion time is for optionally extending the time between packet transfers and port changes to allow a POS-PHY Level 3 Link Layer device enough time to deassert REN and pause the next data transfer.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RLBL7 0 6 RLBL6 0
RSIC3 Receive System Interface Control Register 3 1902
5 RLBL5 0
4 RLBL4 0
3 RLBL3 0
2 RLBL2 0
1 RLBL1 0
0 RLBL0 0
Bits 7 to 0 : Receive System Loopback Bandwidth Limit (RLBL[7:0]) - These eight bits limit the maximum bandwidth of a single port during system loopback. For RLBL[7:0] equals x the bandwidth will be limited to 1/x of the maximum system interface bandwidth. In 8-bit and 16-bit mode, a value of 00h is treated as 01h.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RSIC4 Receive System Interface Control Register 4 1903
5 RMBL5 0
4 RMBL4 0
3 RMBL3 0
2 RMBL2 0
1 RMBL1 0
0 RMBL0 0
Bits 7to 6 : Unused. Must be set = 0 for proper operation. Bit 5 to 0 : Receive Maximum Burst Length (RMBL[5:0]) - In POS-PHY Level 3, these six bits limit the maximum number of four byte data groups that can be transferred from a port before switching to another port. The maximum number of transfers is 2*(RMBL[5:0]+1} in 16-bit mode, and 4*(RMBL[5:0]+1} in 8-bit mode. Note: if no other port is ready to start a transfer, transfer from the current port will continue if the port contains more data than the almost empty level or contains an end of packet. These bits are ignored in POS-PHY Level 2 or UTOPIA mode. A value of 00h disables the maximum burst length.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0 6 -0
RSISRL Receive System Interface Status Register Latched 1904
5 -0
4 -0
3 -0
2 -0
1 -0
0 RCLKAL 0
Bits 7 to 1 : Unused. Bit 0 : Receive System Interface Clock Active Latched (RCLKAL) - This bit is set when RCLK samples the associated receive system interface inputs.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4 Receive T1 Framer Registers Table 11-10 T1 Receive Framer Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0000-00F 0010 0011 0012 0013 0014 0015 0016 - 001F 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046
NAME
FUNCTION
-- RHC RHBSE RDS0SEL RSIGC RCR2 RBOCC -- RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 RSAOI1 RSAOI2 RSAOI3 -- RDMWE1 RDMWE2 RDMWE3 -- RS1 RS2 RS3 RS4 RS5 RS6 RS7
Unused. Must be set = 0 for proper operation. Rx HDLC Control Rx HDLC Bit Suppress Rx DS0 Monitor Select Rx Signaling Control Rx Control 2 Rx BOC Control Unused. Must be set = 0 for proper operation. Rx Idle Definition 1 Rx Idle Definition 2 Rx Idle Definition 3 Rx Idle Definition 4 Rx Idle Definition 5 Rx Idle Definition 6 Rx Idle Definition 7 Rx Idle Definition 8 Rx Idle Definition 9 Rx Idle Definition 10 Rx Idle Definition 11 Rx Idle Definition 12 Rx Idle Definition 13 Rx Idle Definition 14 Rx Idle Definition 15 Rx Idle Definition 16 Rx Idle Definition 17 Rx Idle Definition 18 Rx Idle Definition 19 Rx Idle Definition 20 Rx Idle Definition 21 Rx Idle Definition 22 Rx Idle Definition 23 Rx Idle Definition 24 Rx Sig All Ones Insertion 1 Rx Sig All Ones Insertion 2 Rx Sig All Ones Insertion 3 Unused. Must be set = 0 for proper operation. Rx Digital Milliwatt Enable 1 Rx Digital Milliwatt Enable 2 Rx Digital Milliwatt Enable 3 Unused. Must be set = 0 for proper operation. Rx Signaling 1 Rx Signaling 2 Rx Signaling 3 Rx Signaling 4 Rx Signaling 5 Rx Signaling 6 Rx Signaling 7
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0047 0048 0049 004A 004B 004C - 004F 0050 0051 0052 0053 0054 0055 0056-005F 0060 0061 0062 0063 0064 0065 0066 0067-007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C - 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F 00A0 00A1
NAME
FUNCTION
RS8 RS9 RS10 RS11 RS12 -- LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 -- RDS0M -- RFDL RBOC RSLC1 RSLC2 RSLC3 -- RMMR RCR1 RIBCC RCR3 RIOCR RGCCR ERCNT RHFC RSCC RBICR RBBS -- RLS1 RLS2 RLS3 RLS4 RLS5 -- RLS7 -- RSS1 RSS2 RSS3 -- RSCD1 RSCD2 -- RIIR RIM1 --
Rx Signaling 8 Rx Signaling 9 Rx Signaling 10 Rx Signaling 11 Rx Signaling 12 Unused. Must be set = 0 for proper operation. Rx Line-Code Violation Counter 1 Rx Line-Code Violation Counter 2 Rx Path-Code Violation Count 1 Rx Path-Code Violation Count 2 Rx Frames Out-of-Sync Counter 1 Rx Frames Out-of-Sync Counter 2 Unused. Must be set = 0 for proper operation. Rx DS0 Monitor Unused. Must be set = 0 for proper operation. Rx FDL Rx BOC Rx SLC96 Data Link 1 Rx SLC96 Data Link 2 Rx SLC96 Data Link 3 Unused. Must be set = 0 for proper operation. Rx Master Mode Rx Control 1 Rx In-Band Code Control Rx Control 3 Rx I/O Configuration Rx Gapped Clock Control Rx Error Count Configuration Rx HDLC FIFO Control Unused. Must be set = 0 for proper operation. Rx Spare Code Control Rx BERT Interface Control Rx BERT Bit Suppress En Unused. Must be set = 0 for proper operation. Rx Latched Status 1 Rx Latched Status 2 Rx Latched Status 3 Rx Latched Status 4 Rx Latched Status 5 Unused. Must be set = 0 for proper operation. Rx Latched Status 7 Unused. Must be set = 0 for proper operation. Rx Signaling CoS Status 1 Rx Signaling CoS Status 2 Rx Signaling CoS Status 3 Unused. Must be set = 0 for proper operation. Rx Spare Code Definition 1 Rx Spare Code Definition 2 Unused. Must be set = 0 for proper operation. Rx Interrupt Information Reg Rx Interrupt Mask Reg 1 Unused. Must be set = 0 for proper operation. 169 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7-00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 - 00DF
NAME
FUNCTION
RIM3 RIM4 RIM5 -- RIM7 -- RSCSE1 RSCSE2 RSCSE3 -- RUPCD1 RUPCD2 RDNCD1 RDNCD2 RRTS1 -- RRTS3 -- RRTS5 RHPBA RHF -- RCMR1 RCMR2 RCMR3 RCMR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 -- RBCS1 RBCS2 RBCS3 --
Rx Interrupt Mask Reg 3 Rx Interrupt Mask Reg 4 Rx Interrupt Mask Reg 5 Unused. Must be set = 0 for proper operation. Rx Interrupt Mask Reg 7 Unused. Must be set = 0 for proper operation. Rx Sig CoS Interrupt Enable 1 Rx Sig CoS Interrupt Enable 2 Rx Sig CoS Interrupt Enable 3 Unused. Must be set = 0 for proper operation. Rx Up-Code Definition 1 Rx Up-Code Definition 2 Rx Down-Code Definition 1 Rx Down-Code Definition 2 Rx Real-Time Status 1 Unused. Must be set = 0 for proper operation. Rx Real-Time Status 3 Unused. Must be set = 0 for proper operation. Rx Real-Time Status 5 (HDLC) Rx HDLC Packet Bytes Available Rx HDLC FIFO Unused. Must be set = 0 for proper operation. Rx Channel Mark 1 Rx Channel Mark 2 Rx Channel Mark 3 Rx Channel Mark 4 Rx Signaling Insertion 1 Rx Signaling Insertion 2 Rx Signaling Insertion 3 Rx Signaling Insertion 4 Rx Gapped Clock Channel Select 1 Rx Gapped Clock Channel Select 2 Rx Gapped Clock Channel Select 3 Rx Gapped Clock Channel Select 4 Rx Channel Idle Code Enable 1 Rx Channel Idle Code Enable 2 Rx Channel Idle Code Enable 3 Unused. Must be set = 0 for proper operation. Rx BERT Channel Select 1 Rx BERT Channel Select 2 Rx BERT Channel Select 3 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.1 Receive Master-Mode Register
The receive master-mode register (RMMR) controls the initialization of the receive-side framer. The FRM_EN bit can be left low if the framer for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Address (hex): Bit # Name Default 7 FRM_EN 0
RMMR Receive Master Mode Register 0080, 0280, 0480, 0680
6 INIT_DONE 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 SFTRST 0
0 T1/E1 0
Bit 7 : Framer Enable (FRM_EN). This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled (held in low-power state) 1 = Framer enabled (all features active) Bit 6 : Initialization Done (INIT_DONE). The host (user) must set this bit once the configuration registers have been written. The host is required to write or clear all RAM based registers (addresses 00H to 7FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bits 5 to 2 : Unused. Must be set = 0 for proper operation. Bit 1 : Soft Reset (SFTRST) Level-sensitive processor reset. Should be taken high, then low to reset and initialize the internal processor. 0 = Normal operation 1 = Hold the internal RISC in reset. This bit only affects the receive-side processor. Bit 0 : Receiver T1/E1 Mode Select (T1/E1) This bit sets the operating mode for receiver only! This bit must be set to the desired state before writing INIT_DONE. 0 = T1 operation 1 = E1 operation
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.2 Interrupt Information Register
The interrupt information registers provide an indication of which DS26556 status registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the seven T1 receive status registers is causing the interrupt(s). The interrupt information register bits clear once the appropriate interrupt has been serviced and cleared, as long as no other interrupt condition is present in the associated status register. Status bits that have been masked through the receive-interrupt mask (RIMx) registers are also masked from the RIIR register.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RIIR Receive Interrupt Information Register 009F, 029F, 049F, 069F
6 RLS7 0
5 RLS6 0
4 RLS5 0
3 RLS4 0
2 RLS3 0
1 RLS2* 0
0 RLS1 0
*RLS2 does not create an interrupt, therefore this bit is not used in T1 mode.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.3 T1 Receive Control Registers
These registers provide the primary setup and control of the receive framers. Register Name: Register Description: Address (hex): Bit # Name Default 7 SYNCT 0
RCR1 Receive Control Register 1 0081, 0281, 0481, 0681
6 RB8ZS 0
5 RFM 0
4 ARC 0
3 SYNCC 0
2 RJC 0
1 SYNCE 0
0 RESYNC 0
Bit 7 : Sync Time (SYNCT) 0 = qualify 10 bits 1 = qualify 24 bits Bit 6 : Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 5 : Receive Frame Mode Select (RFM) 0 = ESF framing mode 1 = D4 framing mode Bit 4 : Auto Resync Criteria (ARC) 0 = Resync on OOF or LOS event 1 = Resync on OOF only Bit 3 : Sync Criteria (SYNCC) In D4 Framing Mode: 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern
In ESF Framing Mode: 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6
Bit 2 : Receive Japanese CRC6 Enable (RJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Bit 1 : Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 0 : Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RCR2 Receive Control Register 2 0014, 0214, 0414, 0614
6 -- 0
5 -- 0
4 RSLC96 0
3 OOF2 0
2 OOF1 0
1 RAIIE 0
0 RD4RM 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Receive SLC-96 Synchronizer Enable (RSLC96). See Section 11.4.13. 0 = the SLC-96 synchronizer is disabled 1 = the SLC-96 synchronizer is enable Bits 3, 2 : Out-of-Frame Select Bits (OOF2, OOF1)
OOF2 0 0 1 1 OOF1 0 1 0 1 OUT OF FRAME CRITERIA 2/4 frame bits in error 2/5 frame bits in error 2/6 frame bits in error 2/6 frame bits in error
Bit 1 : Receive RAI Integration Enable (RAIIE) The ESF RAI indication can be interrupted for a period not to exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE causes the RAI status from the DS26556 to be integrated for 200ms. 0 = RAI detects when 16 consecutive patterns of 00FF appear in the FDL. RAI clears when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL. 1 = RAI detects when the condition has been present for greater than 200ms. RAI clears when the condition has been absent for greater than 200ms. Bit 0 : Receive-Side D4 Remote Alarm Select (RD4RM) 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
RCR3 Receive Control Register 3 0083, 0283, 0483, 0683
6 -- 0
5 RSERC 0
4 -- 0
3 -- 0
2 RLB 0
1 PLB 0
0 FLB 0
Bits 7 & 6 : Unused. Must be set = 0 for proper operation. Bit 5 : RSER Control (RSERC) 0 = Allow RSER to output data as received under all conditions (normal operation) 1 = Force RSER to one under loss-of-frame alignment conditions Bits 4 & 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Remote Loopback (RLB) 0 = loopback disabled 1 = loopback enabled Bit 1 : Payload Loopback (PLB) 0 = loopback disabled 1 = loopback enabled Bit 0 : Framer Loopback (FLB) 0 = loopback disabled 1 = loopback enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RCLKINV 0
RIOCR Receive I/O Configuration Register 0084, 0284, 0484, 0684
6 RSYNCINV 0
5 H100EN 0
4 HSCLKM 0
3 RSMS 0
2 RSIO 0
1 RSMS2 0
0 RSMS1 0
Bit 7 : RCLK Invert (RCLKINV) 0 = No inversion 1 = Invert RCLK as input Bit 6 : RSYNC Invert (RSYNCINV) 0 = No inversion 1 = Invert RSYNC output Bit 5 : H.100 SYNC Mode (H100EN) See additional details in Section 8.4.2. 0 = Normal operation 1 = HSSYNC signals are shifted. Note: This bit setting must match TIOCR.HSCLKM Bit 4 : HSYSCLK Mode Select (HSCLKM) 0 = if HSYSCLK is 1.544MHz 1 = if HSYSCLK is 2.048MHz Note: This bit setting must match TIOCR.HSCLKM Bit 3 : RSYNC Multiframe Skip Control (RSMS) This bit is useful in framing format conversions from D4 to ESF. 0 = RSYNC outputs a pulse at every multiframe. 1 = RSYNC outputs a pulse at every other multiframe. Bit 2 : Unused. Must be set = 0 for proper operation. Bit 1 : RSYNC Mode Select 2 (RSMS2) T1: RSYNC pin must be programmed in the output frame mode 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames E1: RSYNC pin must be programmed in the output multiframe mode 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries Bit 0 : RSYNC Mode Select 1 (RSMS1) Selects frame or multiframe pulse when RSYNC pin is in output mode. 0 = frame mode 1 = multiframe mode
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RRTS1 Receive Real-Time Status Register 1 00B0, 02B0, 04B0, 06B0
6 -- 0
5 -- 0
4 -- 0
3 RRAI 0
2 RAIS 0
1 RLOS 0
0 RLOF 0
All bits in this register are real-time (not latched).
Bits 7 to 4 : Unused. Bit 3 : Receive Remote Alarm Indication Condition (RRAI) Set when a remote alarm is received at RPOS and RNEG. Bit 2 : Receive Alarm Indication Signal Condition (RAIS) Set when an unframed all-ones code is received at RPOS and RNEG. Bit 1 : Receive Loss-of-Signal Condition (RLOS) Set when 192 consecutive zeros have been detected at RPOS and RNEG. Bit 0 : Receive Loss-of-Frame Condition (RLOF) Set when the DS26556 is not synchronized to the received data stream.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RRAIC 0
RLS1 Receive Latched Status Register 1 0090, 0290, 0490, 0690
6 RAISC 0
5 RLOSC 0
4 RLOFC 0
3 RRAID 0
2 RAISD 0
1 FLOSD 0
0 RLOFD 0
All bits in this register are latched and can create interrupts.
Bit 7 : Receive Remote Alarm Indication Condition Clear (RRAIC) Falling edge detect of RRAI. Set when a RRAI condition has cleared. Bit 6 : Receive Alarm Indication Signal Condition Clear (RAISC) Falling edge detect of RAIS. Set when a RAIS condition has cleared. Bit 5 : Receive Loss-of-Signal Condition Clear (RLOSC) Falling edge detect of RLOS. Set when an RLOS condition has cleared. Bit 4 : Receive Loss-of-Frame Condition Clear (RLOFC) Falling edge detect of RLOF. Set when an RLOF condition has cleared. Bit 3 : Receive Remote Alarm Indication Condition Detect (RRAID) Rising edge detect of RRAI. Set when a remote alarm is received at RPOS and RNEG. Bit 2 : Receive Alarm Indication Signal Condition Detect (RAISD) Rising edge detect of RAIS. Set when an unframed all-ones code is received at RPOS and RNEG. Bit 1 : Receive Loss-of-Signal Condition Detect (RLOSD) Rising edge detect of RLOS. Set when 192 consecutive zeros have been detected at RPOS and RNEG. Bit 0 : Receive Loss-of-Frame Condition Detect (RLOFD) Rising edge detect of RLOF. Set when the DS26556 has lost synchronized to the received data stream.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RRAIC 0
RIM1 Receive Interrupt Mask Register 1 00A0, 02A0, 04A0, 06A0
6 RAISC 0
5 RLOSC 0
4 RLOFC 0
3 RRAID 0
2 RAISD 0
1 RLOSD 0
0 RLOFD 0
Bit 7 : Receive Remote Alarm Indication Condition Clear (RRAIC) 0 = interrupt masked 1 = interrupt enabled Bit 6 : Receive Alarm Indication Signal Condition Clear (RAISC) 0 = interrupt masked 1 = interrupt enabled Bit 5 : Receive Loss-of-Signal Condition Clear (RLOSC) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive Loss-of-Frame Condition Clear (RLOFC) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive Remote Alarm Indication Condition Detect (RRAID) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive Alarm Indication Signal Condition Detect (RAISD) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive Loss-of-Signal Condition Detect (RLOSD) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Loss-of-Frame Condition Detect (RLOFD) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RPDV 0
RLS2 Receive Latched Status Register 2 0091, 0291, 0491, 0691
6 -- 0
5 COFA 0
4 8ZD 0
3 16ZD 0
2 SEFE 0
1 B8ZS 0
0 FBE 0
All bits in this register are latched. This register does not create interrupts.
Bit 7 : Receive Pulse Density Violation Event (RPDV) Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 6 : Unused. Bit 5 : Change-of-Frame Alignment Event (COFA) Set when the last resync resulted in a change of frame or multiframe alignment. Bit 4 : Eight Zero Detect Event (8ZD) Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RPOS and RNEG. Bit 3 : Sixteen Zero Detect Event (16ZD) Set when a string of at least 16 consecutive zeros (regardless of the length of the string) have been received at RPOS and RNEG. Bit 2 : Severely Errored Framing Event (SEFE) Set when 2 out of 6 framing bits (Ft or FPS) are received in error. Bit 1 : B8ZS Codeword Detect Event (B8ZS) Set when a B8ZS codeword is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not. This bit is useful for automatically setting the line coding. Bit 0 : Frame Bit Error Event (FBE) Set when an Ft (D4) or FPS (ESF) framing bit is received in error.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RRTS3 Receive Real-Time Status Register 3 00B2, 02B2, 04B2, 06B2
6 -- 0
5 -- 0
4 -- 0
3 LORC 0
2 LSP 0
1 LDN 0
0 LUP 0
All bits in this register are real-time (not latched).
Bits 7 to 4 : Unused. Bit 3 : Loss-of-Receive Clock Condition (LORC) Set when the RCLK pin has not transitioned for one channel time. Bit 2 : Spare Code Detected Condition (LSP) Set when the spare code as defined in the RSCD1/2 registers is being received. Bit 1 : Loop-Down Code Detected Condition (LDN) Set when the loop-down code as defined in the RDNCD1/2 register is being received. Bit 0 : Loop-Up Code Detected Condition (LUP) Set when the loop-up code as defined in the RUPCD1/2 register is being received.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex):
RLS3 Receive Latched Status Register 3 0092, 0292, 0492, 0692
Bit # Name Default
7 LORCC 0
6 LSPC 0
5 LDNC 0
4 LUPC 0
3 LORCD 0
2 LSPD 0
1 LDND 0
0 LUPD 0
All bits in this register are latched and can create interrupts.
Bit 7 : Loss-of-Receive Clock Condition Clear (LORCC) Falling edge detect of LORC. Set when a LORC condition was detected and then removed. Bit 6 : Spare Code Detected Condition Clear (LSPC) Falling edge detect of LSP. Set when a spare-code match condition was detected and then removed. Bit 5 : Loop-Down Code Detected Condition Clear (LDNC) Falling edge detect of LDN. Set when a loop-down condition was detected and then removed. Bit 4 : Loop-Up Code Detected Condition Clear (LUPC) Falling edge detect of LUP. Set when a loop-up condition was detected and then removed. Bit 3 : Loss of Receive Clock Condition Detect (LORCD) Rising edge detect of LORC. Set when the RCLK pin has not transitioned for one channel time. Bit 2 : Spare Code Detected Condition Detect (LSPD) Rising edge detect of LSP. Set when the spare code as defined in the RSCD1/2 registers is being received. Bit 1 : Loop-Down Code Detected Condition Detect (LDND) Rising edge detect of LDN. Set when the loopdown code as defined in the RDNCD1/2 register is being received. Bit 0 : Loop-Up Code Detected Condition Detect (LUPD) Rising edge detect of LUP. Set when the loop-up code as defined in the RUPCD1/2 register is being received.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 LORCC 0
RIM3 Receive Interrupt Mask Register 3 00A2, 02A2, 04A2, 06A2
6 LSPC 0
5 LDNC 0
4 LUPC 0
3 LORCD 0
2 LSPD 0
1 LDND 0
0 LUPD 0
Bit 7 : Loss-of-Receive Clock Condition Clear (LORCC) 0 = interrupt masked 1 = interrupt enabled Bit 6 : Spare Code Detected Condition Clear (LSPC) 0 = interrupt masked 1 = interrupt enabled Bit 5 : Loop-Down Code Detected Condition Clear (LDNC) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Loop-Up Code Detected Condition Clear (LUPC) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Loss-of-Receive Clock Condition Detect (LORCD) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Spare Code Detected Condition Detect (LSPD) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Loop-Down Code Detected Condition Detect (LDND) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Loop-Up Code Detected Condition Detect (LUPD) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
RLS4 Receive Latched Status Register 4 0093, 0293, 0493, 0693
6 0
5 0
4 -- 0
3 RSCOS 0
2 1SEC 0
1 TIMER 0
0 RMF 0
All bits in this register are latched and can create interrupts.
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Receive Signaling Change-of-State Event (RSCOS) Set when any channel selected by the receive signaling change-of-state interrupt-enable registers (RSCSE1 through RSCSE3), changes signaling state. Bit 2 : One-Second Timer (1SEC) Set on every one-second interval based on RCLK. Bit 1 : Timer Event (TIMER) Follows the error counter update interval as determined by the ECUS bit in the error counter configuration register (ERCNT). T1: Set on increments of 1 second or 42ms based on RCLK. E1: Set on increments of 1 second or 62.5ms based on RCLK. Bit 0 : Receive Multiframe Event (RMF) Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
RIM4 Receive Interrupt Mask Register 4 00A3, 02A3, 04A3, 06A3
6 0
5 0
4 0
3 RSCOS 0
2 1SEC 0
1 TIMER 0
0 RMF 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Receive Signaling Change-of-State Event (RSCOS) 0 = interrupt masked 1 = interrupt enabled Bit 2 : One-Second Timer (1SEC) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Timer Event (TIMER) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RLS7 Receive Latched Status Register 7 0096, 0296, 0496, 0696
6 -- 0
5 RRAI-CI 0
4 RAIS-CI 0
3 RSLC96 0
2 RFDLF 0
1 BC 0
0 BD 0
All bits in this register are latched and can create interrupts.
Bits 6 & 7 : Unused. Bit 5 : Receive RAI-CI Detect (RRAI-CI) Set when an RAI-CI pattern has been detected by the receiver (see Section 11.5.1). This bit is active in ESF-framing mode only, and sets only if an RAI condition is being detected (RRTS1.3). When the host reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1 seconds). Bit 4 : Receive AIS-CI Detect (RAIS-CI) Set when an AIS-CI pattern has been detected by the receiver (see Section 11.5.1). This bit is set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host, and sets again each time the AIS-CI pattern is detected (approximately every 1.2 seconds). Bit 3 : Receive SLC-96 Alignment Event (RSLC96) Set when a valid SLC-96 alignment pattern is detected in the fs-bit stream, and the RSLCx registers have data available for retrieval (Section 11.12). Bit 2 : Receive FDL Register Full Event (RFDLF) Set when the 8-bit RFDL register is full. Useful for SLC-96 operation, or manual extraction of FDL data bits (Sections 11.12 and 11.13). Bit 1 : BOC Clear Event (BC) Set when a valid BOC is no longer detected (with the disintegration filter applied). (Section 11.11) Bit 0 : BOC Detect Event (BD) Set when a valid BOC has been detected (with the BOC filter applied) (Section 11.11)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RIM7 Receive Interrupt Mask Register 7 (BOC/FDL) 00A6, 02A6, 04A6, 06A6
6 -- 0
5 RRAI-CI 0
4 RAIS-CI 0
3 RSLC96 0
2 RFDLF 0
1 BC 0
0 BD 0
Bits 6 & 7 : Unused. Must be set = 0 for proper operation. Bit 5 : Receive RAI-CI (RRAI-CI) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive AIS-CI (RAIS-CI) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive SLC-96 (RSLC96) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive FDL Register Full (RFDLF) 0 = interrupt masked 1 = interrupt enabled Bit 1 : BOC Clear Event (BC) 0 = interrupt masked 1 = interrupt enabled Bit 0 : BOC Detect Event (BD) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
RDMWE1 T1 Receive-Digital Milliwatt-Enable Register 1 003C, 023C, 043C, 063C
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 0 to 7 : Receive-Digital Milliwatt Enable for Channels 8 to 1 (CH8 to CH1) 0 = Do not affect the receive data associated with this channel. 1 = Replace the receive data associated with this channel with digital milliwatt code.
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
RDMWE2 T1 Receive-Digital Milliwatt-Enable Register 2 003D, 023D, 043D, 063D
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 0 to 7 : Receive-Digital Milliwatt Enable for Channels 16 to 9 (CH16 to CH9) 0 = Do not affect the receive data associated with this channel. 1 = Replace the receive data associated with this channel with digital milliwatt code.
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
RDMWE3 T1 Receive-Digital Milliwatt-Enable Register 3 003E, 023E, 043E, 063E
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 0 to 7 : Receive-Digital Milliwatt Enable for Channels 1 to 24 (CH24 to CH17) 0 = Do not affect the receive data associated with this channel. 1 = Replace the receive data associated with this channel with digital milliwatt code.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 1SECS 0
ERCNT Error Counter Configuration Register 0086, 0286, 0486, 0886
6 MCUS 0
5 MECU 0
4 ECUS 0
3 EAMS 0
2 FSBE 0
1 MOSCRF 0
0 LCVCRF 0
Bit 7 : One-Second Select (1SECS) When timed update is enabled by EAMS, setting this bit for a specific framer allows that framer's counters to latch on the one-second reference from Framer #1. 0 = Use internally generated one-second timer. 1 = Use one-second timer from Framer #1. Bit 6 : Manual Counter Update Select (MCUS) When manual update mode is enabled with EAMS, this bit can be used to allow the GLCE bit in GCR1 to latch all counters. Useful for synchronously latching counters of multiple framers. 0 = MECU is used to manually latch counters. 1 = GLCE is used to manually latch counters. Bit 5 : Manual Error Counter Update (MECU) When enabled by ERCNT.3, the changing of this bit from 0 to 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 250ms before reading the error count registers to allow for proper update. Bit 4 : Error Counter Update Select (ECUS) T1 mode: 0 = Update error counters once a second 1 = Update error counters every 42ms (336 frames) E1 mode: 0 = Update error counters once a second 1 = Update error counters every 62.5ms (500 frames) Bit 3 : Error Accumulation Mode Select (EAMS) 0 = ERCNT.4 determines accumulation time (timed update) 1 = ERCNT.5 determines accumulation time (manual update) Bit 2 : PCVCR Fs-Bit Error Report Enable (FSBE) 0 = do not report bit errors in Fs-bit position; only Ft bit position 1 = report bit errors in Fs-bit position as well as Ft bit position Bit 1 : Multiframe Out-of-Sync Count Register Function Select (MOSCRF) 0 = count errors in the framing bit position 1 = count the number of out-of-sync multiframes Bit 0 : T1 Line-Code Violation Count Register Function Select (LCVCRF) 0 = do not count excessive zeros 1 = count excessive zeros
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.4 T1 Line-Code Violation Count Register (LCVCR)
T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not disabled during receive loss-of-synchronization (RLOF = 1) conditions. See Table 11-11 for details of exactly what the LCVCRs count.
Table 11-11 T1 Line-Code Violation Counting Options
COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (RCR1.6) No No Yes Yes WHAT IS COUNTED IN THE LCVCRs
BPVs BPVs + 16 consecutive zeros BPVs (B8ZS codewords not counted) BPVs + 8 consecutive zeros
Register Name: Register Description: Address (hex): Bit # Name Default 7 LCVC15 0
LCVCR1 Line-Code Violation Count Register 1 0050, 0250, 0450, 0650
6 LCVC14 0
5 LCVC13 0
4 LCVC12 0
3 LCVC11 0
2 LCVC10 0
1 LCVC9 0
0 LCCV8 0
Bits 7 to 0 : Line-Code Violation Counter Bits 15 to 8 (LCVC15 to LCVC8) LCV15 is the MSB of the 16-bit code violation count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 LCVC7 0
LCVCR2 Line-Code Violation Count Register 2 0051, 0251, 0451, 0651
6 LCVC6 0
5 LCVC5 0
4 LCVC4 0
3 LCVC3 0
2 LCVC2 0
1 LCVC1 0
0 LCVC0 0
Bits 7 to 0 : Line-Code Violation Counter Bits 7 to 0 (LCVC7 to LCVC0) LCV0 is the LSB of the 16-bit code violation count
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.5 T1 Path-Code Violation Count Register (PCVCR)
The path-code violation count register records either Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position. Through the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR is disabled during receive loss-of-synchronization (RLOF = 1) conditions. See Table 11-12 for a detailed description of exactly what errors the PCVCR counts.
Table 11-12 T1 Path-Code Violation Counting Arrangements
FRAMING MODE COUNT Fs ERRORS? WHAT IS COUNTED IN THE PCVCRs Errors in the Ft pattern Errors in both the Ft & Fs patterns Errors in the CRC6 codewords
D4 D4 ESF
No Yes Don't Care
Register Name: Register Description: Address (hex): Bit # Name Default 7 PCVC15 0
PCVCR1 Path-Code Violation Count Register 1 0052, 0252, 0452, 0652
6 PCVC14 0
5 PCVC13 0
4 PCVC12 0
3 PCVC11 0
2 PCVC10 0
1 PCVC9 0
0 PCVC8 0
Bits 7 to 0 : Path-Code Violation Counter Bits 15 to 8 (PCVC15 to PCVC8) PCVC15 is the MSB of the 16-bit path-code violation count
Register Name: Register Description: Address (hex): Bit # Name Default 7 PCVC7 0
PCVCR2 Path-Code Violation Count Register 2 0053, 0253, 0453, 0653
6 PCVC6 0
5 PCVC5 0
4 PCVC4 0
3 PCVC3 0
2 PCVC2 0
1 PCVC1 0
0 PCVC0 0
Bits 7 to 0 : Path-Code Violation Counter Bits 7 to 0 (PCVC7 to PCVC0) PCVC0 is the LSB of the 16-bit pathcode violation count.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.6 T1 Frames Out-of-Sync Count Register (FOSCR)
The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOF = 1) conditions. The FOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is disabled during receive loss-of-synchronization (RLOF = 1) conditions. See Table 11-13 for a detailed description of what the FOSCR is capable of counting.
Table 11-13 T1 Frame Out-of-Sync Counting Arrangements
FRAMING MODE (RCR1.5) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (ERCNT.1) MOS F-Bit MOS F-Bit WHAT IS COUNTED IN THE FOSCRs Number of multiframes out of sync Errors in the Ft pattern Number of multiframes out of sync Errors in the FPS pattern
Register Name: Register Description: Address (hex): Bit # Name Default 7 FOS15 0
FOSCR1 Frames Out-of-Sync Count Register 1 0054, 0254, 0454, 0654
6 FOS14 0
5 FOS13 0
4 FOS12 0
3 FOS11 0
2 FOS10 0
1 FOS9 0
0 FOS8 0
Bits 7 to 0 : Frames Out-of-Sync Counter Bits 15 to 8 (FOS15 to FOS8) FOS15 is the MSB of the 16-bit frames out-of-sync count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 FOS7 0
FOSCR2 Frames Out-of-Sync Count Register 2 0055, 0255, 0455, 0655
6 FOS6 0
5 FOS5 0
4 FOS4 0
3 FOS3 0
2 FOS2 0
1 FOS1 0
0 FOS0 0
Bits 7 to 0 : Frames Out-of-Sync Counter Bits 7 to 0 (FOS7 to FOS0) FOS0 is the LSB of the 16-bit frames outof-sync count.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.7 DS0 Monitoring Function
The DS26556 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the receive DS0 (RDS0M) register. The RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1 channel. T1 channels 1 through 24 map to register values 0 through 23. For example, if DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into RDS0SEL: RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0 Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RDS0SEL Receive-Channel Monitor Select 0012, 0212, 0412, 0612
6 -- 0
5 -- 0
4 RCM4 0
3 RCM3 0
2 RCM2 0
1 RCM1 0
0 RCM0 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bits 4 to 0 : Receive-Channel Monitor Bits (RCM4 to RCM0) RCM0 is the LSB of a 5-bit channel select that determines which receive-DS0 channel data appears in the RDS0M register.
Register Name: Register Description: Address (hex): Bit # Name Default 7 B1 0
RDS0M Receive-DS0 Monitor Register 0060, 0260, 0460, 0660
6 B2 0
5 B3 0
4 B4 0
3 B5 0
2 B6 0
1 B7 0
0 B8 0
Bits 7 to 0 : Receive-DS0 Channel Bits (B1 to B8) Receive-channel data that has been selected by the receivechannel monitor select register. B8 is the LSB of the DS0 channel (last bit to be received).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.8 Receive Signaling Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RSIGC Receive Signaling Control Register 0013, 0213, 0413, 0613
6 -- 0
5 -- 0
4 RFSA1 0
3 -- 0
2 RSFF 0
1 RSFE 0
0 RSIE 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Receive-Force Signaling All Ones (RFSA1) 0 = do not force robbed bit signaling to all ones 1 = force signaling bits to all ones on a per-channel basis according to the RSAOI1-RSAOI3 registers Bit 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Receive-Signaling Force Freeze (RSFF). Freezes receive-side signaling at RSIG (and RSER if receivesignaling reinsertion is enabled); overrides receive-freeze enable (RFE). 0 = do not force a freeze event 1 = force a freeze event Bit 1 : Receive-Signaling Freeze Enable (RSFE) 0 = no freezing of receive-signaling data occurs 1 = allow freezing of receive-signaling data at RSIG (and RSER if receive-signaling reinsertion is enabled) Bit 0 : Receive-Signaling Integration Enable (RSIE) 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for three multiframes for a change of state to be reported
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RSI1, RSI2, RSI3, RSI4 Receive-Signaling Reinsertion Enable Registers 00C8, 02C8, 04C8, 06C8
Setting any of the CH1 through CH24 bits in the RSI1 through RSI3 registers causes signaling data to be reinserted for the associated channel. RSI4 is used for 2.048MHz backplane operation.
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1 CH9 CH17 CH25
RSI1 RSI2 RSI3 RSI4*
Register Name: Register Description: Address (hex):
RSAOI1, RSAOI2, RSAOI3, Receive-Signaling All-Ones Insertion Registers 0038 to 003A, 0238 to 023A, 0438 to 043A, 0638 to 063A
Setting any of the CH1 through CH24 bits in the RSAOI1 through RSAOI3 registers causes signaling data to be replaced with logic ones as received at the backplane.
(MSB) CH8 CH16 CH24
CH7 CH15 CH23
CH6 CH14 CH22
CH5 CH13 CH21
CH4 CH12 CH20
CH3 CH11 CH19
CH2 CH10 CH18
(LSB) CH1 CH9 CH17
RSAOI1 RSAOI2 RSAOI3
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RS1 to RS12 Receive Signaling Registers 0040 to 004B, 0240 to 024B, 0440 to 044B, 0640 to 064B
In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the framer repeats the A and B signaling data in the C and D bit locations. Therefore, when the framer is operated in D4 framing mode, the user needs to retrieve the signaling bits every 1.5ms as opposed to 3ms for ESF mode. The receive-signaling registers are frozen and not updated during a loss-of-sync condition. They contain the most recent signaling information before the OOF occurred.
(MSB) CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A
CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B
CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C
CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D
CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A
CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B
CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C
(LSB) CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D
RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RSS1, RSS2, RSS3 Receive Signaling Status Registers 0098 to 009A, 0298 to 029A, 0498, to 049A
When a channel's signaling data changes state, the respective bit in registers RSS1-RSS3 is set and latched. The RSCOS bit (RLSR4.3) is set if the channel was also enabled by setting the appropriate bit in RSCSE1-3. The INT signal goes low if enabled by the interrupt mask bit RIM4.3. Bit # Name Name Name Default 7 CH8 CH16 CH24 0 6 CH7 CH15 CH23 0 5 CH6 CH14 CH22 0 4 CH5 CH13 CH21 0 3 CH4 CH12 CH20 0 2 CH3 CH11 CH19 0 1 CH2 CH10 CH18 0 0 CH1 CH9 CH17 0
RSS1 RSS2 RSS3
Note: Status bits in this register are latched.
Register Name: Register Description: Address (hex):
RSCSE1, RSCSE2, RSCSE3 Receive-Signaling Change-of-State Enable 00A8 to 00AA, 02A8 to 02AA, 04A8, to 04AA
Setting any of the CH1 through CH24 bits in the RSS1 through RSS3 registers cause RSCOS (RLSR4.3) to be set when that channel's signaling data changes state. Bit # Name Name Name Default 7 CH8 CH16 CH24 0 6 CH7 CH15 CH23 0 5 CH6 CH14 CH22 0 4 CH5 CH13 CH21 0 3 CH4 CH12 CH20 0 2 CH3 CH11 CH19 0 1 CH2 CH10 CH18 0 0 CH1 CH9 CH17 0
RSCSE1 RSCSE2 RSCSE3
11.4.9 T1 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Twenty-four receive idle definition registers (RIDR1-RIDR24) are provided to set the 8-bit idle code for each channel. The receive-channel idle code-enable registers (RCICE1-3) are used to enable idle code replacement on a per-channel basis. The receive-channel idle code-enable registers (RCICE1/2/3) are used to determine which of the 24 T1 channels from the T1 line to the backplane should be overwritten with the code placed in the receive idle-code definition register. Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RIDR1 to RIDR24 Receive Idle-Code Definition Registers 1 to 24 0020 to 0037, 0220 TO 0237, 0420 to 0437, 0620 to 0637
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bits 7 to 0 : Per-Channel Idle Code Bits (C7 to C0) C0 is the LSB of the code (this bit is transmitted last). Address 20H is for channel 1; address 37H is for channel 24.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Name Name Default 7 CH8 CH16 CH24 0
RCICE1, RCICE2, RCICE3 Receive-Channel Idle Code-Enable Registers 00D0 to 00D2, 02D0 to 02D2, 04D0 to 04D2, 06D0 t0 06D2
6 CH7 CH15 CH23 0
5 CH6 CH14 CH22 0
4 CH5 CH13 CH21 0
3 CH4 CH12 CH20 0
2 CH3 CH11 CH19 0
1 CH2 CH10 CH18 0
0 CH1 CH9 CH17 0
RCICE1 RCICE2 RCICE3
Bits 7 to 0 : Receive Channels 24 to 1 Code Insertion Control Bits (CH24 to CH1) 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream
11.4.10 T1 Receive Channel Mark Registers
The Receive Channel Mark Registers (RCMR1/RCMR2/RCMR3/RCMR4) control the mapping of channels to the receive cell/packet interface and the RCHMRK pin. The RCHMRK signal is used internally to select which channels will be mapped to the receive cell/packet interface. Externally, the signal can be used to multiplex TDM data out of channels not used by the receive cell/packet interface. When the appropriate bits are set to 1, the receive cell/packet function is mapped to that channel and externally the RCHMRK pin is held high during the entire corresponding channel time. In T1 mode, only RCMR1 to RCMR3 and the LSB of RCMR4 are used. Register Name: Register Description: Address (hex):
(MSB) CH8 CH16 CH24 RCMR1, RCMR2, RCMR3 Receive-Channel Mark Registers 1 to 3 00C4 to 00C6, 02C4 to 02C6, 04C4 to 04C6, 06C4 to 06C6 (LSB) CH1 CH9 CH17
CH7 CH15 CH23
CH6 CH14 CH22
CH5 CH13 CH21
CH4 CH12 CH20
CH3 CH11 CH19
CH2 CH10 CH18
RCMR1 RCMR2 RCMR3
Bits 7 to 0 : Receive Channels 24 to 1 Channel Mark Control Bits (CH24 to CH1) 0 = force the RCHMRK pin to remain low during this channel time 1 = force the RCHMRK pin high during this channel time
Register Name: Register Description: Address (hex):
(MSB)
RCMR4 Receive-Channel Mark Register 4 00C7, 02C7, 04C7, 06C7 (LSB) RFBIT
RCMR4
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Receive F Bit (RFBIT) RCMR4.0 = 0, RCHMRK low during the F-bit RCMR4.0 = 1, RCHMRK high during the F-bit
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RCCF 0
RGCCR Receive Gapped Clock Control Register 0085, 0285, 0485, 0685
6 RGCE 0
5 0
4 0
3 0
2 0
1 0
0 0
Bit 7 : Receive Channel Clock Format (RCCF) This bit controls the function of the RCHMRK pin went it is in the channel clock mode and the RGCCR.6 bit is set = 1. Channel clock mode is enabled in the RCHMRK Pin Function Select (RPFS) register. 0 = 64kbps, clock output during all 8 bits 1 = 56kbps, clock output during 7 MSBs Bit 6 :/ Receive Gapped Clock Enable (RGCE) This bit controls the function of the RCHMRK pin went it is in the channel clock mode. Channel clock mode is enabled in the RCHMRK Pin Function Select (RPFS) register. 0 = RCHMRK outputs a pulse during the LSB of each channel time. 1 = RCHMRK outputs a gapped bit clock as selected by the RGCCS1 through RGCCC4 registers. Bits 5 to 0 : Unused. Must be set = 0 for proper operation.
11.4.11 Receive Fractional T1 Support (Gapped-Clock Mode)
Register Name: Register Description: Address (hex):
(MSB) CH8 CH16 CH24 CH32 RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive-Gapped-Clock Channel-Select Registers 00CC to 00CF, 02CC to 02CF, 04CC to 04CF, 06CC to 06CF (LSB) CH1 CH9 CH17 CH25/F-Bit
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
RGCCS1 RGCCS2 RGCCS3 RGCCS4*
Bits 7 to 0 : Receive Channels 1 to 32 Gapped-Clock Channel Select Bits (CH1 to CH32) These bits control the RCHMRK pin when it is in the channel clock mode. Channel clock mode is enabled in the RCHMRK Pin Function Select (RPFS) register. 0 = no clock is present on RCHMRK during this channel time 1 = force a clock on RCHMRK during this channel time. The clock will be synchronous with RCLK. Note that RGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on RCHMRK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on RCHMRK during the F-bit time: RGCCS4.0 = 0: do not generate a clock during the F-bit RGCCS4.0 = 1: generate a clock during the F-bit In this mode, RGCCS4.1--RGCCS4.7 should be set to 0.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.12 Receive T1 Bit-Oriented Code (BOC) Controller
Register Name: Register Description: Address (hex): Bit # Name Default 7 RBR 0
RBOCC Receive BOC Control Register 0015, 0215, 0415, 0615
6 -- 0
5 RBD1 0
4 RBD0 0
3 -- 0
2 RBF1 0
1 RBF0 0
0 -- 0
Bit 7 :Receive-BOC Reset (RBR) A 0-to-1 transition resets the BOC circuitry. Must be cleared and set again for a subsequent reset. Modifications to the RBF0, RBF1, RBD0, and RBD1 bits are not applied to the BOC controller until a BOC reset has been completed. Bit 6 : Unused. Must be set = 0 for proper operation. Bits 5 to 4 : Receive-BOC-Disintegration Bits (RBD0, RBD1) The BOC Disintegration filter sets the number of message bits that must be received without a valid BOC in order to set the BC bit indicating that a valid BOC is no longer being received.
RBD1 0 0 1 1 RBD0 0 1 0 1 Consecutive Message Bits for BOC Clear Identification 16 32 48 64 (Note 1)
Bit 3 : Unused. Must be set = 0 for proper operation. Bits 2 to 1 : Receive-BOC-Filter Bits (RBF0, RBF1) The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message.
RBF1 0 0 1 1 RBF0 0 1 0 1 Consecutive BOC Codes for Valid Sequence Identification None 3 5 7 (Note 1)
Bit 0 : Unused. Must be set = 0 for proper operation. Note 1: The DS26556's BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be detected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RBOC Receive BOC Register 0063, 0263, 0463, 0663
6 -- 0
5 RBOC5 0
4 RBOC4 0
3 RBOC3 0
2 RBOC2 0
1 RBOC1 0
0 RBOC0 0
The RBOC Register always contains the last valid BOC received.
Bits 7, 6 : Unused Bit 5 : BOC Bit 5 (RBOC5) Bit 4 : BOC Bit 4 (RBOC4) Bit 3 : BOC Bit 3 (RBOC3) Bit 2 : BOC Bit 2 (RBOC2) Bit 1 : BOC Bit 1 (RBOC1) Bit 0 : BOC Bit 0 (RBOC0)
11.4.13 Receive SLC-96 Operation
Register Name: Register Description: Address (hex):
(MSB) C8 M2 S=1 RSLC1, RSLC2, RSLC3 Receive SLC96 Data Link Registers 0064 to 0066, 0264 to 0266, 0464 to 0466, 0664 to 0666 (LSB) C1 C9 M3
C7 M1 S4
C6 S=0 S3
C5 S=1 S2
C4 S=0 S1
C3 C11 A2
C2 C10 A1
RSLC1 RSLC2 RSLC3
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.14 Receive FDL
Register Name: Register Description: Address (hex): Bit # Name Default 7 RFDL7 0
RFDL Receive FDL Register 0062, 0262, 0462, 0662
6 RFDL6 0
5 RFDL5 0
4 RFDL4 0
3 RFDL3 0
2 RFDL2 0
1 RFDL1 0
0 RFDL0 0
The receive FDL register (RFDL) reports the incoming facility data link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL updates on multiframe boundaries and reports the six Fs bits in RFDL0- RFDL5.
Bit 7 : Receive FDL Bit 7 (RFDL7) MSB of the received FDL code. Bit 6 : Receive FDL Bit 6 (RFDL6) Bit 5 : Receive FDL Bit 5 (RFDL5) Bit 4 : Receive FDL Bit 4 (RFDL4) Bit 3 : Receive FDL Bit 3 (RFDL3) Bit 2 : Receive FDL Bit 2 (RFDL2) Bit 1 : Receive FDL Bit 1 (RFDL1) Bit 0 : Receive FDL Bit 0 (RFDL0) LSB of the received FDL code.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.15 Programmable In-Band Loop-Code Detection
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RIBCC Receive In-Band Code Control Register 0082, 0282, 0482, 0682
6 -- 0
5 RUP2 0
4 RUP1 0
3 RUP0 0
2 RDN2 0
1 RDN1 0
0 RDN0 0
Bits 7 & 6 : Unused. Must be set = 0 for proper operation. Bits 5 to 3 : Receive-Up-Code Length Definition Bits (RUP0 to RUP2) RUP2 RUP1 RUP0 Length Selected (bits) 1 2 3 4 5 6 7 8 / 16
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Bits 2 to 0 : Receive-Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 RDN1 RDN0 Length Selected (bits) 1 2 3 4 5 6 7 8 / 16
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RUPCD1 Receive-Up Code-Definition Register 1 00AC, 02AC, 04AC, 06AC
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Note: Writing this register resets the detector's integration period.
Bit 7 : Receive-Up Code-Definition Bit 7 (C7) First bit of the repeating pattern. Bit 6 : Receive-Up Code-Definition Bit 6 (C6) A don't care if a 1-bit length is selected. Bit 5 : Receive-Up Code-Definition Bit 5 (C5) A don't care if a 1- or 2-bit length is selected. Bit 4 : Receive-Up Code-Definition Bit 4 (C4) A don't care if a 1- to 3-bit length is selected. Bit 3 : Receive-Up Code-Definition Bit 3 (C3) A don't care if a 1- to 4-bit length is selected. Bit 2 : Receive-Up Code-Definition Bit 2 (C2) A don't care if a 1- to 5-bit length is selected. Bit 1 : Receive-Up Code-Definition Bit 1 (C1) A don't care if a 1- to 6-bit length is selected. Bit 0 : Receive-Up Code-Definition Bit 0 (C0) A don't care if a 1- to 7-bit length is selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RUPCD2 Receive-Up Code-Definition Register 2 00AD, 02AD, 04AD, 06AD
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bit 7 : Receive-Up Code-Definition Bit 7 (C7) A don't care if a 1- to 7-bit length is selected. Bit 6 : Receive-Up Code-Definition Bit 6 (C6) A don't care if a 1- to 7-bit length is selected. Bit 5 : Receive-Up Code-Definition Bit 5 (C5) A don't care if a 1- to 7-bit length is selected. Bit 4 : Receive-Up Code-Definition Bit 4 (C4) A don't care if a 1- to 7-bit length is selected. Bit 3 : Receive-Up Code-Definition Bit 3 (C3) A don't care if a 1- to 7-bit length is selected. Bit 2 : Receive-Up Code-Definition Bit 2 (C2) A don't care if a 1- to 7-bit length is selected. Bit 1 : Receive-Up Code-Definition Bit 1 (C1) A don't care if a 1- to 7-bit length is selected. Bit 0 : Receive-Up Code-Definition Bit 0 (C0) A don't care if a 1- to 7-bit length is selected.
Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RDNCD1 Receive-Down Code-Definition Register 1 00AE, 02AE, 04AE, 06AE
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Note: Writing this register resets the detector's integration period.
Bit 7 : Receive-Down Code-Definition Bit 7 (C7) First bit of the repeating pattern. Bit 6 : Receive-Down Code-Definition Bit 6 (C6) A don't care if a 1-bit length is selected. Bit 5 : Receive-Down Code-Definition Bit 5 (C5) A don't care if a 1- or 2-bit length is selected. Bit 4 : Receive-Down Code-Definition Bit 4 (C4) A don't care if a 1- to 3-bit length is selected. Bit 3 : Receive-Down Code-Definition Bit 3 (C3) A don't care if a 1- to 4-bit length is selected. Bit 2 : Receive-Down Code-Definition Bit 2 (C2) A don't care if a 1- to 5-bit length is selected. Bit 1 : Receive-Down Code-Definition Bit 1 (C1) A don't care if a 1- to 6-bit length is selected. Bit 0 : Receive-Down Code-Definition Bit 0 (C0) A don't care if a 1- to 7-bit length is selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RDNCD2 Receive-Down Code-Definition Register 2 00AF, 02AF, 04AF, 06AF
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bit 7 : Receive-Down Code-Definition Bit 7 (C7) A don't care if a 1- to 7-bit length is selected. Bit 6 : Receive-Down Code-Definition Bit 6 (C6) A don't care if a 1- to 7-bit length is selected. Bit 5 : Receive-Down Code-Definition Bit 5 (C5) A don't care if a 1- to 7-bit length is selected. Bit 4 : Receive-Down Code-Definition Bit 4 (C4) A don't care if a 1- to 7-bit length is selected. Bit 3 : Receive-Down Code-Definition Bit 3 (C3) A don't care if a 1- to 7-bit length is selected. Bit 2 : Receive-Down Code-Definition Bit 2 (C2) A don't care if a 1- to 7-bit length is selected. Bit 1 : Receive-Down Code-Definition Bit 1 (C1) A don't care if a 1- to 7-bit length is selected. Bit 0 : Receive-Down Code Definition Bit 0 (C0) A don't care if a 1- to 7-bit length is selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RSCC In-Band Receive-Spare Control Register
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 RSC2 0
1 RSC1 0
0 RSC0 0
Bits 2 to 0 : Receive-Spare Code-Length Definition Bits (RSC0 to RSC2) RSC2 0 0 0 0 1 1 1 1 RSC1 0 0 1 1 0 0 1 1 RSC0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8 / 16
Bits 7 to 3 : Unused. Must be set = 0 for proper operation.
Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RSCD1 Receive-Spare Code-Definition Register 1 009C, 029C, 049C, 069C
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Note: Writing this register resets the detector's integration period.
Bit 7 : Receive-Spare Code-Definition Bit 7 (C7) First bit of the repeating pattern. Bit 6 : Receive-Spare Code-Definition Bit 6 (C6) A don't care if a 1-bit length is selected. Bit 5 : Receive-Spare Code-Definition Bit 5 (C5) A don't care if a 1- or 2-bit length is selected. Bit 4 : Receive-Spare Code-Definition Bit 4 (C4) A don't care if a 1- to 3-bit length is selected. Bit 3 : Receive-Spare Code-Definition Bit 3 (C3) A don't care if a 1- to 4-bit length is selected. Bit 2 : Receive-Spare Code-Definition Bit 2 (C2) A don't care if a 1- to 5-bit length is selected. Bit 1 : Receive-Spare Code-Definition Bit 1 (C1) A don't care if a 1- to 6-bit length is selected. Bit 0 : Receive-Spare Code-Definition Bit 0 (C0) A don't care if a 1- to 7-bit length is selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RSCD2 Receive-Spare Code-Definition Register 2 009D, 029D, 049D, 069D
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bit 7 : Receive-Spare Code-Definition Bit 7 (C7) A don't care if a 1- to 7-bit length is selected. Bit 6 : Receive-Spare Code-Definition Bit 6 (C6) A don't care if a 1- to 7-bit length is selected. Bit 5 : Receive-Spare Code-Definition Bit 5 (C5) A don't care if a 1- to 7-bit length is selected. Bit 4 : Receive-Spare Code-Definition Bit 4 (C4) A don't care if a 1- to 7-bit length is selected. Bit 3 : Receive-Spare Code-Definition Bit 3 (C3) A don't care if a 1- to 7-bit length is selected. Bit 2 : Receive-Spare Code-Definition Bit 2 (C2) A don't care if a 1- to 7-bit length is selected. Bit 1 : Receive-Spare Code-Definition Bit 1 (C1) A don't care if a 1- to 7-bit length is selected. Bit 0 : Receive-Spare Code-Definition Bit 0 (C0) A don't care if a 1- to 7-bit length is selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.16 Receive HDLC Controller
Register Name: Register Description: Address (hex): Bit # Name Default 7 RCRCD 0
RHC Receive HDLC Control Register 0010, 0210, 0410, 0610
6 RHR 0
5 RHMS 0
4 RHCS4 0
3 RHCS3 0
2 RHCS2 0
1 RHCS1 0
0 RHCS0 0
Bit 7 : Receive CRC16 Display (RCRCD) 0 = Do not write received CRC16 code to FIFO 1= Write received CRC16 code to FIFO after last octet of packet Bit 6 : Receive HDLC Reset (RHR) Resets the receive-HDLC controller and flushes the receive FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset receive HDLC controller and flush the receive FIFO Bit 5 : Receive HDLC Mapping Select (RHMS) 0 = Receive HDLC assigned to channels 1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode) Bit 4 to Bit 0 : Receive HDLC Channel Select (RHCSx) These bits determine which DS0 is mapped to the HDLC controller when enabled with RHMS = 0. RHCS0 to RHCS4 = all zeros selects channel 1, RHCS0 to RHCS4 = all ones selects channel 32 (E1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 BSE8 0
RHBSE Receive HDLC Bit Suppress Register 0011, 0211, 0411, 0611
6 BSE7 0
5 BSE6 0
4 BSE5 0
3 BSE4 0
2 BSE3 0
1 BSE2 0
0 BSE1 0
Bit 7 : Receive Channel Bit 8 Suppress (BSE8) MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Receive Channel Bit 7 Suppress (BSE7) Set to one to stop this bit from being used. Bit 5 : Receive Channel Bit 6 Suppress (BSE6) Set to one to stop this bit from being used. Bit 4 : Receive Channel Bit 5 Suppress (BSE5) Set to one to stop this bit from being used. Bit 3 : Receive Channel Bit 4 Suppress (BSE4) Set to one to stop this bit from being used. Bit 2 : Receive Channel Bit 3 Suppress (BSE3) Set to one to stop this bit from being used. Bit 1 : Receive Channel Bit 2 Suppress (BSE2) Set to one to stop this bit from being used. Bit 0 : Receive Channel Bit 1 Suppress (BSE1) LSB of the channel. Set to one to stop this bit from being used.
11.4.16.1 Receive HDLC FIFO Control Control of the receive FIFO is accomplished through the receive-HDLC FIFO control (RHFC). The FIFO control register sets the watermarks for the receive FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) is set. RHWM is a real-time bit and remains set as long as the receive FIFO's write pointer is above the watermark. If enabled, this condition can also cause an interrupt through the INT pin. Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RHFC Receive HDLC FIFO Control Register 0087, 0287, 0487, 0687
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 RFHWM1 0
0 RFHWM0 0
Bits 7 to 2 : Unused. Must be set = 0 for proper operation. Bits 1 to 0 : Receive FIFO High Watermark Select (RFHWM0 to RFHWM1) RFHWM1 RFHWM0 Receive FIFO Watermark (bytes) 4 16 32 48
0 0 1 1
0 1 0 1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.16.2 Receive HDLC Packet Bytes Available The lower 6 bits of the receive-packet-bytes-available register indicates the number of bytes (0 through 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value refers to one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register, the host then checks the HDLC status registers for detailed message status.
If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message, then the MSB of the RHPBA register returns a 1. This indicates that the host may safely read the number of bytes returned by the lower 6 bits of the RHPBA register, but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise). Register Name: Register Description: Address (hex): Bit # Name Default 7 MS 0
RHPBA Receive HDLC Packet Bytes Available Register 00B5, 02B5, 04B5, 06B5
6 RPBA6 0
5 RPBA5 0
4 RPBA4 0
3 RPBA3 0
2 RPBA2 0
1 RPBA1 0
0 RPBA0 0
Bit 7 : Message Status (MS) 0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC Status register for details. 1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the HDLC status. Bits 6-0 : Receive FIFO Packet Bytes Available Count (RPBA0 to RPBA6) RPBA0 is the LSB.
Register Name: Register Description: Address (hex): Bit # Name Default 7 RHD7 0
RHF Receive HDLC FIFO Register 00B6, 02B6, 04B6, 06B6
6 RHD6 0
5 RHD5 0
4 RHD4 0
3 RHD3 0
2 RHD2 0
1 RHD1 0
0 RHD0 0
Bit 7 : Receive HDLC Data Bit 7 (RHD7) MSB of a HDLC packet data byte. Bit 6 : Receive HDLC Data Bit 6 (RHD6) Bit 5 : Receive HDLC Data Bit 5 (RHD5) Bit 4 : Receive HDLC Data Bit 4 (RHD4) Bit 3 : Receive HDLC Data Bit 3 (RHD3) Bit 2 : Receive HDLC Data Bit 2 (RHD2) Bit 1 : Receive HDLC Data Bit 1 (RHD1) Bit 0 : Receive HDLC Data Bit 0 (RHD0) LSB of a HDLC packet data byte.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.16.3 HDLC Status and Information RRTS5 and RLS5 provide status information for the receive HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. With the latched bits, when an event occurs and a bit is set to 1, it remains set until the user reads that bit. The bit is cleared when it is read and it is not set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched.
Like the other latched-status registers, the user follows a read of the status bit with a write. The byte written to the register informs the device which of the latched bits the user wishes to clear (the real-time bits are not affected by writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions the user wishes to clear and a zero in the bit positions the user wishes not to clear. The HDLC status register RLS5 can initiate a hardware interrupt through the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin through the receive-HDLC interrupt-mask register (RIM5). Interrupts force the INT signal low when the event occurs. The INT pin is allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RRTS5 Receive Real-Time Status Register 5 (HDLC) 00B4, 02B4, 04B4, 06B4
6 PS2 0
5 PS1 0
4 PS0 0
3 -- 0
2 -- 0
1 RHWM 0
0 RNE 0
Note: All bits in this register are real-time. Bit 7 : Unused. Bits 6 to 4 : Receive Packet Status (PS2 to PS0) These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 PS1 PS0 PACKET STATUS In Progress: End of message has not yet been reached. Packet OK: Packet ended with correct CRC codeword. CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword. Abort: Packet ended because an abort signal was detected (seven or more ones in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
Bits 3 & 2 : Unused. Bit 1 : Receive-FIFO Above High-Watermark Condition (RHWM) Set when the receive 64-byte FIFO fills beyond the high watermark as defined by the receive-HDLC FIFO control register (RHFC).This is a real-time bit. Bit 0 : Receive-FIFO Not Empty Condition (RNE) Set when the receive 64-byte FIFO has at least one byte available for a read. This is a real-time bit.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RLS5 Receive Latched Status Register 5 (HDLC) 0094, 0295, 0494, 0694
6 -- 0
5 ROVR 0
4 RHOBT 0
3 RPE 0
2 RPS 0
1 RHWMS 0
0 RNES 0
Note: All bits in this register are latched and can cause interrupts.
Bits 7 & 6 : Unused. Bit 5 : Receive FIFO Overrun (ROVR) Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bit 4 : Receive HDLC Opening Byte Event (RHOBT) Set when the next byte available in the receive FIFO is the first byte of a message. Bit 3 : Receive Packet End Event (RPE) Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and is cleared when read. Bit 2 : Receive Packet Start Event (RPS) Set when the HDLC controller detects an opening byte. This is a latched bit and will be cleared when read. Bit 1 : Receive-FIFO Above High-Watermark Set Event (RHWMS) Set when the receive-64-byte FIFO crosses the high watermark as defined by the receive HDLC FIFO control register (RHFC). Rising edge detect of RHWM. Bit 0 : Receive-FIFO Not Empty Set Event (RNES) Set when the receive FIFO has transitioned from `empty' to `not-empty' (at least one byte has been put into the FIFO). Rising edge detect of RNE.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RIM5 Receive Interrupt Mask 5 (HDLC) 00A4, 02A4, 04A4, 06A4
6 -- 0
5 ROVR 0
4 RHOBT 0
3 RPE 0
2 RPS 0
1 RHWMS 0
0 RNES 0
Bits 7 & 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Receive-FIFO Overrun (ROVR) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive-HDLC Opening-Byte Event (RHOBT) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive-Packet-End Event (RPE) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive-Packet-Start Event (RPS) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive-FIFO Above High-Watermark Set Event (RHWMS) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive-FIFO Not Empty Set Event (RNES) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.4.17 Receive BERT
Data from the DS26556 receive framer can be ported to the on-chip BERT by using the registers described below. Either framed or unframed data can be provided to the BERT, controlled by the RBFUS bit in the RBICR. Any single DS0 or combination of DS0s can be extracted from the data stream up to the entire T1 payload, as controlled by the RBCS registers. Note that one BERT resource is shared among all 8 framers. Therefore, the RBEN bit should be set for only one framer at a time. If multiple framers have the RBEN bit set, the lower number framer is assigned the resource. Details concerning the BERT can be found in Section 13.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RBICR Receive BERT Interface Control Register 008A, 028A, 048A, 068A
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 RBDC 0
1 RBFUS 0
0 RBEN 0
Bits 7 to 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Receive BERT Direction Control (RBDC) 0 = Receive Path: The BERT receives data from the network side via RPOS and RNEG. 1 = Backplane: The BERT receives data from the system backplane via the TSER pin. Bit 1 : Receive BERT Framed/Unframed Select (RBFUS) 0 = The framer does not provide data from the F-bit position (framed). 1 = The framer clocks data from the F-bit position (unframed). Bit 0 : Receive BERT Enable (RBEN) 0 = Receive BERT is not assigned to this framer. 1 = Receive BERT is assigned to this framer.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RBCS1, RBCS2, RBCS3 Receive BERT Channel Select Registers 00D4 to 00D6, 02D4 to 02D6, 04D4 to 04D6, 06D4 to 06D6
Setting any of the CH1 through CH24 bits in the RBCS1 through RBCS3 registers maps data from those channels to the on-board BERT. RBEN must be set to 1 for these registers to function. Multiple or all channels can be selected simultaneously. These registers affect the receive-side framer only.
(MSB) CH8 CH16 CH24
CH7 CH15 CH23
CH6 CH14 CH22
CH5 CH13 CH21
CH4 CH12 CH20
CH3 CH11 CH19
CH2 CH10 CH18
(LSB) CH1 CH9 CH17
RBCS1 RBCS2 RBCS3
Register Name: Register Description: Address (hex): Bit # Name Default 7 BSE8 0
RBBS Receive BERT Bit Suppress Register 008B, 028B, 048B, 068B
6 BSE7 0
5 BSE6 0
4 BSE5 0
3 BSE4 0
2 BSE3 0
1 BSE2 0
0 BSE1 0
Bit 7 : Receive Channel Bit 8 Suppress (BSE8) Bit 6 : Receive Channel Bit 7 Suppress (BSE7) Bit 5 : Receive Channel Bit 6 Suppress (BSE6) Bit 4 : Receive Channel Bit 5 Suppress (BSE5) Bit 3 : Receive Channel Bit 4 Suppress (BSE4) Bit 2 : Receive Channel Bit 3 Suppress (BSE3) Bit 1 : Receive Channel Bit 2 Suppress (BSE2) Bit 0 : Receive Channel Bit 1 Suppress (BSE1)
MSB of the channel. Set to one to stop this bit from being used. Set to one to stop this bit from being used. Set to one to stop this bit from being used. Set to one to stop this bit from being used Set to one to stop this bit from being used. Set to one to stop this bit from being used. Set to one to stop this bit from being used. LSB of the channel. Set to one to stop this bit from being used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5 T1 Transmit framer Table 11-14 T1 Transmit Framer Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0100-010F 0110 0111 0112 0113 0114 - 0117 0118 0119 011A 011B - 011F 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 0130 0131 0132 0133 0134 0135 0136 0137 0138-013F 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 014A
NAME
FUNCTION
-- THC1 THBSE -- THC2 -- SSIE1 SSIE2 SSIE3 -- TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 -- TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11
Unused. Must be set = 0 for proper operation Tx HDLC Control 1 Tx HDLC Bit Suppress Unused. Must be set = 0 for proper operation Tx HDLC Control 2 Unused. Must be set = 0 for proper operation Tx Software Signaling Insertion Enable 1 Tx Software Signaling Insertion Enable 2 Tx Software Signaling Insertion Enable 3 Unused. Must be set = 0 for proper operation Tx Idle Definition 1 Tx Idle Definition 2 Tx Idle Definition 3 Tx Idle Definition 4 Tx Idle Definition 5 Tx Idle Definition 6 Tx Idle Definition 7 Tx Idle Definition 8 Tx Idle Definition 9 Tx Idle Definition 10 Tx Idle Definition 11 Tx Idle Definition 12 Tx Idle Definition 13 Tx Idle Definition 14 Tx Idle Definition 15 Tx Idle Definition 16 Tx Idle Definition 17 Tx Idle Definition 18 Tx Idle Definition 19 Tx Idle Definition 20 Tx Idle Definition 21 Tx Idle Definition 22 Tx Idle Definition 23 Tx Idle Definition 24 Unused. Must be set = 0 for proper operation Tx Signaling 1 Tx Signaling 2 Tx Signaling 3 Tx Signaling 4 Tx Signaling 5 Tx Signaling 6 Tx Signaling 7 Tx Signaling 8 Tx Signaling 9 Tx Signaling 10 Tx Signaling 11 216 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 014B 014C - 014F 0150 0151 0152 0153-0161 0162 0163 0164 0165 0166 0167-017F 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 0190 0191 0192 0193-019E 019F 01A0 01A1 01A2 01A3-01AB 01AC 01AD 01AE 01AF 01B0 01B1 01B2 01B3 01B4 01B5-01BA 01BB 01BC-01C3 01C4 01C5
NAME
FUNCTION
TS12 -- TCICE1 TCICE2 TCICE3 -- TFDL TBOC TSLC1 TSLC2 TSLC3 -- TMMR TCR1 TCR2 TCR3 TIOCR TGCCR TCR4 THFC TDS0SEL TBICR TBBS -- -- TSYNCC TLS1 TLS2 TLS3 -- TIIR TIM1 TIM2 TIM3 -- TCD1 TCD2 -- -- -- TRTS2 -- TFBA THF -- TDS0M -- TCMR1 TCMR2
Tx Signaling 12 Unused. Must be set = 0 for proper operation. Tx Channel Idle Code Enable 1 Tx Channel Idle Code Enable 2 Tx Channel Idle Code Enable 3 Unused. Must be set = 0 for proper operation. Tx FDL Tx BOC Tx SLC96 Data Link 1 Tx SLC96 Data Link 2 Tx SLC96 Data Link 3 Unused. Must be set = 0 for proper operation. Tx Master Mode Tx Control 1 Tx Control 2 Tx Control 3 Tx I/O Configuration Tx Gapped Clock Control Tx Control 4 Tx HDLC FIFO Control Unused. Must be set = 0 for proper operation. Tx DS0 Monitor Select Tx BERT Interface Control Tx BERT Bit Suppress Enable Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Tx Synchronizer Control Unused. Must be set = 0 for proper operation Tx Latched Status 1 Tx Latched Status 2 (HDLC) Tx Latched Status 3 (SYNC) Unused. Must be set = 0 for proper operation Tx Interrupt Information Register Tx Interrupt Mask Register 1 Tx Interrupt Mask Register 2 (HDLC) Tx Interrupt Mask Register 3 (SYNC) Unused. Must be set = 0 for proper operation Tx Code Definition 1 Tx Code Definition 2 Unused. Must be set = 0 for proper operation Unused. Must be set = 0 for proper operation Unused. Must be set = 0 for proper operation Tx Real-Time Status Register 2 (HDLC) Unused. Must be set = 0 for proper operation Tx HDLC FIFO Buffer Available Tx HDLC FIFO Unused. Must be set = 0 for proper operation Tx DS0 Monitor Unused. Must be set = 0 for proper operation Tx Channel Mark 1 Tx Channel Mark 2 217 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 01C6 01C7 01C8 01C9 01CA 01CB 01CC 01CD 01CE 01CF 01D0 01D1 01D2 01D3 01D4 01D5 01D6 01D7 - 01FF
NAME
FUNCTION
TCMR3 TCMR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 -- TBPCS1 TBPCS2 TBPCS3 --
Tx Channel Mark 3 Tx Channel Mark 4 Tx Hardware Signaling Channel Select 1 Tx Hardware Signaling Channel Select 2 Tx Hardware Signaling Channel Select 3 Tx Hardware Signaling Channel Select 4 Tx Gapped Clock Channel Select 1 Tx Gapped Clock Channel Select 2 Tx Gapped Clock Channel Select 3 Tx Gapped Clock Channel Select 4 Per-Channel Loopback Enable 1 Per-Channel Loopback Enable 2 Per-Channel Loopback Enable 3 Unused. Must be set = 0 for proper operation Tx BERT Channel Select 1 Tx BERT Channel Select 2 Tx BERT Channel Select 3 Unused. Must be set = 0 for proper operation
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.1 Transmit-Master Mode Register
The transmit-master mode register (TMMR) controls the initialization of the transmit-side formatter. The FRM_EN bit may be left `low' if the formatter for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Address (hex): Bit # Name Default 7 FRM_EN 0
TMMR Transmit Master Mode Register 0180
6 INIT_DONE 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 SFTRST 0
0 T1/E1 0
Bit 7 : Framer Enable (FRM_EN) This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled (held in low-power state) 1 = Framer enabled (all features active) Bit 6 : Initialization Done (INIT_DONE) The host (user) must set this bit once he/she has written the configuration registers. The host is required to write or clear all RAM based registers (addresses 100H to 17FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bits 5 to 2 : Unused. Must be set = 0 for proper operation. Bit 1 : Soft Reset (SFTRST) Level-sensitive processor reset. Should be taken high then low to reset and initialize the internal processor. 0 = Normal operation 1 = Hold the internal RISC in reset. This bit only affects the transmit-side processor. Bit 0 : Transmitter T1/E1 Mode Select (T1/E1) Sets operating mode for transmitter only! This bit must be written with the desired value prior to setting INIT_DONE. 0 = T1 operation 1 = E1 operation
11.5.2 Interrupt Information Registers
The interrupt information registers provide an indication of which DS26556 status registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt has been serviced and cleared. Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TIIR Transmit Interrupt Information Register 019F
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 TLS3 0
1 TLS2 0
0 TLS1 0
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.3 T1 Transmit Control Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 TJC 0
TCR1 Transmit Control Register 1 0181
6 TFPT 0
5 TCPT 0
4 TSSE 0
3 GB7S 0
2 TB8ZS 0
1 TAIS 0
0 TRAI 0
Bit 7 : Transmit Japanese CRC6 Enable (TJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Bit 6 : Transmit F-Bit Pass-Through (TFPT) 0 = F bits sourced internally 1 = F bits sampled at TSER Bit 5 : Transmit CRC Pass-Through (TCPT) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time Bit 4 : Transmit-Software Signaling Enable (TSSE) 0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still define which channels are to have B7 stuffing performed. 1 = source signaling data as enabled by the SSIEx registers. Bit 3 : Global Bit 7 Stuffing (GB7S) 0 = allow the SSIEx registers to determine which channels containing all zeros are to be bit 7 stuffed 1 = force bit 7 stuffing in all-zero byte channels regardless of how the SSIEx registers are programmed Bit 2 : Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 1 : Transmit Alarm Indication Signal (TAIS) 0 = transmit data normally 1 = transmit an unframed all-ones code Bit 0 : Transmit Remote Alarm Indication (TRAI) 0 = do not transmit remote alarm 1 = transmit remote alarm
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TFDLS 0
TCR2 Transmit Control Register 2 0182
6 TSLC96 0
5 -- 0
4 FBCT2 0
3 FBCT1 0
2 TD4RM 0
1 PDE 0
0 TB7ZS 0
Bit 7 : TFDL Register Select (TFDLS) 0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6) 1 = source FDL or Fs bits from the internal HDLC controller Bit 6 : Transmit SLC-96 (TSLC96) Set this bit to a one in SLC-96 framing applications. Must be set to source the SLC-96 alignment pattern and data from the TSLC1-3 registers. See Section 11.4.9 for details. 0 = SLC-96 insertion disabled 1 = SLC-96 insertion enabled Bit 5 : Unused. Must be set = 0 for proper operation. Bit 4 : F Bit Corruption Type 2 (FBCT2) Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Bit 3 : F Bit Corruption Type 1 (FBCT1) A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization. Bit 2 : Transmit D4 RAI Select (TD4RM) 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 Bit 1 : Pulse Density Enforcer Enable (PDE) The framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive zeros and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the transmit and receive data streams are reported in the TLS1.3 and RLS2.7 bits respectively. When this bit is set to one, the DS26556 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer Bit 0 : Transmit Side Bit 7 Zero Suppression Enable (TB7ZS) 0 = no stuffing occurs 1 = force bit 7 to a one as determined by the GB7S bit at TCR1.3
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TCR3 Transmit Control Register 3 0183
6 0
5 TCSS1 0
4 TCSS0 0
3 0
2 TFM 0
1 IBVD 0
0 TLOOP 0
Bits 7 & 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Transmit Clock Source Select Bit 1 (TCSS1) TCSS1 TCSS0 Transmit Clock Source
0 0 1 1
0 1 0 1
The TCLK pin is always the source of Transmit Clock. Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after 1 channel time. For Future Use Use the signal present at RCLK as the Transmit Clock. The TCLK pin is ignored.
Bit 4 : Transmit Clock Source Select Bit 0 (TCSS0) Bit 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Transmit Frame Mode Select (TFM) 0 = ESF framing mode 1 = D4 framing mode Bit 1 : Insert BPV (IBPV) A 0-to-1 transition on this bit will cause a single BiPolar Violation (BPV) to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 0 : Transmit Loop-Code Enable (TLOOP) See Section 11.4.10 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TCR4 Transmit Control Register 4 0186
6 -- 0
5 -- 0
4 -- 0
3 TRAIM 0
2 TAISM 0
1 TC1 0
0 TC0 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Transmit RAI Mode (TRAIM) Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = transmit normal RAI upon activation with TCR1.0 1 = transmit RAI-CI (T1.403) upon activation with TCR1.0 Bit 2 : Transmit AIS Mode (TAISM) Determines the pattern sent when TAIS (TCR1.1) is activated. 0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1 1 = transmit AIS-CI (T1.403) upon activation with TCR1.1 Bits 1 to 0 : Transmit Code Length Definition Bits (TC0 to TC1) TC1 0 0 1 1 TC0 0 1 0 1 Length Selected (bits) 5 6/3 7 16 / 8 / 4 / 2 / 1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TCLKINV 0
TIOCR Transmit I/O Configuration Register 0184
6 TSYNCINV 0
5 HSSYNCINV 0
4 HSCLKM 0
3 HSSM 0
2 TSIO 0
1 TSDW 0
0 TSM 0
Bit 7 : TCLK Invert (TCLKINV) 0 = No inversion 1 = Invert Bit 6 : TSYNC Invert (TSYNCINV) 0 = No inversion 1 = Invert Bit 5 : HSSYNC Invert (HSSYNCINV) 0 = No inversion 1 = Invert Bit 4 : HSYSCLK Mode Select (HSCLKM) 0 = if HSYSCLK is 1.544MHz 1 = if HSYSCLK is 2.048/4.096/8.192/16.384MHz Note: This bit setting must match RIOCR.HSCLKM. Bit 3 : HSSYNC Mode Select (HSSM) Selects frame or multiframe mode for the HSSYNC pin. 0 = frame mode 1 = multiframe mode Bit 2 : TSYNC I/O Select (TSIO) 0 = TSYNC is an input 1 = TSYNC is an output Bit 1 : TSYNC Doublewide (TSDW) (Note: This bit must be set to zero when TSYNC is an input (TSIO=0) or when TSYNC is in multiframe output mode (TSM = 1). 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames Bit 0 : TSYNC Mode Select (TSM) Selects frame or multiframe mode for the TSYNC pin. Valid when TSYNC is an output. 0 = frame mode 1 = multiframe mode
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.4 T1 Transmit Status and Information
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INT signal.
Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real time bits will remain stable, and valid during the host read operation. The current value of the internal status signals can be read at any time from the real time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a `change-of-state' for an alarm, condition, or event; and operate in a read-thenwrite fashion. The user should read the value of the desired status bit, and then write a `1' to that particular bit location in order to clear the latched value (write a `0' to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (TIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs. The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin will clear even if the alarm is still present.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TLS1 Transmit Latched Status Register 1 0190, 0390, 0590, 0790
6 0
5 0
4 TSLC96 0
3 TPDV 0
2 TMF 0
1 LOTCC 0
0 LOTC 0
All bits in this register are latched and can cause interrupts.
Bits 7 to 5: Unused. Bit 4 : Transmit SLC96 Multiframe Event (TSLC96) When enabled by TCR2.6, this bit will set once per SLC96 multiframe (72 frames) to alert the host that new data may be written to the TSLC1-TSLC3 registers. See section 11.5.13. Bit 3 : Transmit Pulse Density Violation Event (TPDV) Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 2 : Transmit Multiframe Event (TMF) Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. Bit 1 : Loss of Transmit Clock Condition Clear (LOTCC) Set when the LOTC condition has cleared (a clock has been sensed at the TCLK pin). Bit 0 : Loss of Transmit Clock Condition (LOTC) Set when the TCLK pin has not transitioned for approximately 3 clock periods. Will force the LOTC pin high if enabled. This bit can be cleared by the host even if the condition is still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit.
If enabled by TIM1.0, the INT pin will transition low when this bit is set, and transition high when this bit is cleared (if no other unmasked interrupt conditions exist).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TIM1 Transmit Interrupt Mask Register 1 01A0, 03A0, 05A0, 07A0
6 0
5 0
4 TSLC96 0
3 TPDV 0
2 TMF 0
1 LOTCC 0
0 LOTC 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Transmit SLC96 Multiframe Event (TSLC96) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Transmit Pulse Density Violation Event (TPDV) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Transmit Multiframe Event (TMF) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Loss of Transmit Clock Clear Condition (LOTCC) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Loss of Transmit Clock Condition (LOTC) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.5 T1 Per-Channel Loopback
Each of the bit position in the Per-Channel Loopback Registers (PCLR1/PCLR2/PCLR3) represent a DS0 channel in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSER for that channel. Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
PCL1 Per-Channel Loopback Enable Register 1 01D0, 03D0, 05D0, 07D0
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 : Per-Channel Loopback Enable for Channels 1 to 24 (CH8 to CH1) 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
PCL2 Per-Channel Loopback Enable Register 2 01D1, 03D1, 05D1, 07D1
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 : Per-Channel Loopback Enable for Channels 1 to 24 (C16 to CH9) 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
PCL3 Per-Channel Loopback Enable Register 3 01D2, 03D2, 05D2, 07D2
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 : Per-Channel Loopback Enable for Channels 1 to 24 (CH24 to CH17) 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.6 T1 Transmit DS0 Monitoring Function
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TDS0SEL Transmit DS0 Channel Monitor Select 0189, 0389, 0589, 0789
6 -- 0
5 -- 0
4 TCM4 0
3 TCM3 0
2 TCM2 0
1 TCM1 0
0 TCM0 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bits 4 to 0 : Transmit Channel Monitor Bits (TCM0 to TCM4) TCM0 is the LSB of a 5 bit channel select that determines which transmit channel data will appear in the TDS0M register.
Register Name: Register Description: Address (hex): Bit # Name Default 7 B1 0
TDS0M Transmit DS0 Monitor Register 01BB, 03BB, 05BB, 07BB
6 B2 0
5 B3 0
4 B4 0
3 B5 0
2 B6 0
1 B7 0
0 B8 0
Bits 7 to 0 : Transmit DS0 Channel Bits (B1 to B8) Transmit channel data that has been selected by the Transmit Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
11.5.7 T1 Transmit Signaling Operation
Register Name: Register Description: Address (hex):
(MSB) CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A TS1 TO TS12 Transmit Signaling Registers (T1 MODE) 0140 - 014B, 0340 - 034B, 0540 - 054B, 0740 - 074B (LSB) CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D
CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B
CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C
CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D
CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A
CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B
CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C
TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12
Note: In D4 framing mode, the C and D bits are not used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
SSIE1 Software Signaling Insertion Enable Register 1 0118, 0318, 0518, 0718
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 8 to 8 (CH8 to CH1) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
SSIE2 Software Signaling Insertion Enable Register 2 0119, 0319, 0519, 0719
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 16 to 9 (CH16 TO CH9) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
SSIE3 Software Signaling Insertion Enable Register 3 011A, 031A, 051A, 071A
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 24 to 17 (CH24 TO CH17) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
THSCS1 Transmit Hardware Signaling Channel Select Register 1 01C8, 03C8, 05C8, 07C8
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 8 to 1 (CH8 to CH1). This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
THSCS2 Transmit Hardware Signaling Channel Select Register 2 01C9, 03C9, 05C9, 07C9
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 16 to 9 (CH16 to CH9). This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
THSCS3 Transmit Hardware Signaling Channel Select Register 3 01CA, 03CA, 05CA, 07CA
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 24 to 17 (CH24 to CH17 This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH32 0
THSCS4 Transmit Hardware Signaling Channel Select Register 4 01CB, 03CB, 05CB, 07CB
6 CH31 0
5 CH30 0
4 CH29 0
3 CH28 0
2 CH27 0
1 CH26 0
0 CH25 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 32 to 25 (CH32 to CH25). This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.8 T1 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Twenty-four Transmit Idle Definition Registers (TIDR1-TIDR24) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-3) are used to enable idle code replacement on a per channel basis. Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
TIDR1 to TIDR24 Transmit Idle Code Definition Registers 1 to 24 0120 to 0137, 0320 to 0337, 0520 to 0537, 0720 to 0737
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bits 7 to 0 : Per-Channel Idle Code Bits (C0 to C7) C0 is the LSB of the Code (this bit is transmitted last). Address 120H is for channel 1, address 137H is for channel 24. The Transmit Channel Idle Code Enable Registers (TCICE1/2/3) are used to determine which of the 24 T1 channels from the backplane should be overwritten with the code placed in the Transmit Idle Code Definition Register.
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
TCICE1 Transmit Channel Idle Code Enable Register 1 0150, 0350, 0550, 0750
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 : Transmit Channels 8 to 1 Code Insertion Control Bits (CH8 to CH1) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
TCICE2 Transmit Channel Idle Code Enable Register 2 0151, 0351, 0551, 0751
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 : Transmit Channels 16 to 9 Code Insertion Control Bits (CH16 to CH9) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
TCICE3 Transmit Channel Idle Code Enable Register 3 0152, 0352, 0552, 0752
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 : Transmit Channels 24 to 17 Code Insertion Control Bits (CH24 to CH17) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.9 T1 Transmit Channel Mark Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
TCMR1 Transmit Channel Mark Register 1 01C4, 03C4, 05C4, 07C4
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 : Transmit Channels 8 to 8 Channel Mark Control Bits (CH8 to CH1) 0 = force the TCHMRK pin to remain low during this channel time 1 = force the TCHMRK pin high during this channel time
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
TCMR2 Transmit Channel Mark Register 2 01C5, 03C5, 05C5, 07C5
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 : Transmit Channels 16 to 9 Channel Mark Control Bits (CH16 to CH9) 0 = force the TCHMRK pin to remain low during this channel time 1 = force the TCHMRK pin high during this channel time
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
TCMR3 Transmit Channel Mark Register 3 01C6, 03C6, 05C6, 07C6
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 : Transmit Channels 24 to 17 Channel Mark Control Bits (CH24 to CH17) 0 = force the TCHMRK pin to remain low during this channel time 1 = force the TCHMRK pin high during this channel time In T1 mode, the LSB of TCMR4 determines whether or not the TCHMRK signal will pulse high during the F-Bit time:
Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TCMR4 Transmit Channel Mark Register 4 01C7, 03C7, 05C7, 07C7
6 0
5 0
4 0
3 0
2 0
1 0
0 T1FBM 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : T1 F-Bit Mark (T1FBM) In T1 mode, the LSB of TCMR4 determines whether or not the TCHMRK signal will pulse high during the F-Bit time: 0 = do not pulse TCHMRK during the F-Bit 1 = pulse TCHMRK during the F-Bit
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TDATFMT 0
TGCCR Transmit Gapped Clock Control Register 185h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 TGCLKEN 0
5 0
4 0
3 0
2 0
1 0
0 0
Bit 7 : Transmit Channel Data Format (TDATFMT) 0 = 64KBps (data contained in all 8 bits) 1 = 56KBps (data contained in 7 out of the 8 bits) Bit 6 : Transmit Gapped Clock Enable (TGPCKEN) If the TCHMRK pin is in the channel clock mode then this bit determines if TCHMRK outputs a pulse during the LSB of all channels or a gapped clock during selected channels. 0 = pulse during LSB of all 1 = gapped clock during selected channels Bits 5 to 0 : Unused. Must be set = 0 for proper operation.
11.5.10 Fractional T1 Support (Gapped Clock Mode)
The DS26556 can be programmed to output gapped clocks for selected channels in transmit path. When the TCHMRK pin is in the channel clock mode and gapped channel clock is enabled, a gated clock is output on the TCHMRK pin during selected channel times. The channel selection is controlled via the transmit-gapped-clock channel-select registers (TGCCS1-TGCCS4). If TCHMRK is in the channel clock mode clock mode is enabled by the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). Register Name: Register Description: Address (hex):
(MSB) CH8 CH16 CH24 CH32 TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 1CCh, 1CDh, 1CEh, 1CFh [+ (200h x n) : where n = 0 to 3, for Ports 1 to 4] (LSB) CH1 CH9 CH17 CH25/Fbit
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TGCCS1 TGCCS2 TGCCS3 TGCCS4*
Bits 7 to 0 : Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32) 0 = no clock is present on TCHMRK during this channel time 1 = output a clock on TCHMRK during this channel time. The clock will be synchronous with TCLK. * Note that TGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the 'gapped' clock on TCHMRK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on TCHMRK during the F-Bit time: TGCCS4.0 = 0, do not generate a clock during the F-Bit TGCCS4.0 = 1, generate a clock during the F-Bit In this mode, TGCCS4.1 to TGCCS4.7 should be set to 0.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.11 T1 Transmit Bit Oriented Code (BOC) Controller
The DS26556 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Bits 0 through 5 in the TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6) causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as SBOC is set. Note that the TFPT (TCR1.6) control bit must be set to 'zero' for the BOC message to overwrite F-bit information being sampled on TSER.
To Transmit a BOC 1) Write 6-bit code into the TBOC register. 2) Set SBOC bit in THC2 = 1.
Register Name: Register Description: Address (hex): Bit # Name Default 7 --0
TBOC Transmit BOC Register 163h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 TBOC5 0
4 TBOC4 0
3 TBOC3 0
2 TBOC2 0
1 TBOC1 0
0 TBOC0 0
Bits 7 & 6 : Unused, must be set = 0 for proper operation. Bit 5 : Transmit BOC Bit 5 (TBOC5) MSB of the Transmit BOC Code. Bit 4 : Transmit BOC Bit 4 (TBOC4) Bit 3 : Transmit BOC Bit 3 (TBOC3) Bit 2 : Transmit BOC Bit 2 (TBOC2) Bit 1 : Transmit BOC Bit 1 (TBOC1) Bit 0 : Transmit BOC Bit 0 (TBOC0). LSB of the Transmit BOC Code.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.12 T1 Transmit FDL
Register Name: Register Description: Address (hex): Bit # Name Default 7 TFDL7 0
TFDL Transmit FDL Register 162h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 TFDL6 0
5 TFDL5 0
4 TFDL4 1
3 TFDL3 1
2 TFDL2 1
1 TFDL1 0
0 TFDL0 0
Note: Also used to insert Fs framing pattern in D4 framing mode.
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
Bit 7 : Transmit FDL Bit 7 (TFDL7) MSB of the Transmit FDL Code. Bit 6 : Transmit FDL Bit 6 (TFDL6) Bit 5 : Transmit FDL Bit 5 (TFDL5) Bit 4 : Transmit FDL Bit 4 (TFDL4) Bit 3 : Transmit FDL Bit 3 (TFDL3) Bit 2 : Transmit FDL Bit 2 (TFDL2) Bit 1 : Transmit FDL Bit 1 (TFDL1) Bit 0 : Transmit FDL Bit 0 (TFDL0) LSB of the Transmit FDL Code.
11.5.13 Transmit SLC-96 Operation
Register Name: Register Description: Address (hex):
(MSB) C8 M2 S=1 TSLC1, TSLC2, TSLC3 Transmit SLC96 Data Link Registers 164h, 165h, 166h [+ (200h x n) : where n = 0 to 3, for Ports 1 to 4] (LSB) C1 C9 M3
C7 M1 S4
C6 S=0 S3
C5 S=1 S2
C4 S=0 S1
C3 C11 A2
C2 C10 A1
TSLC1 TSLC2 TSLC3
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.14 Transmit HDLC Controller
Register Name: Register Description: Address (hex): Bit # Name Default 7 NOFS 0
THC1 Transmit HDLC Control Register 1 110h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 TEOML 0
5 THR 0
4 THMS 0
3 TFS 0
2 TEOM 0
1 TZSD 0
0 TCRCD 0
Bit 7 : Number of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Bit 6 : Transmit End of Message and Loop (TEOML) To loop on a message, should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to the end of all messages. Bit 5 : Transmit HDLC Reset (THR) Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset transmit HDLC controller and flush the transmit FIFO Bit 4 : Transmit HDLC Mapping Select (THMS) 0 = Transmit HDLC assigned to channels 1 = Transmit HDLC assigned to FDL(T1 mode), Sa Bits(E1 mode) Bit 3 : Transmit Flag/Idle Select (TFS) This bit selects the inter-message fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 2 : Transmit End of Message (TEOM) Should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a 2byte CRC code to the end of the message. Bit 1 : Transmit Zero Stuffer Defeat (TZSD) The Zero Stuffer function automatically inserts a zero in the message field (between the flags) after 5 consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (de-stuffs) any zero after 5 ones in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Bit 0 : Transmit CRC Defeat (TCRCD) A 2-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TABT 0
THC2 Transmit HDLC Control Register 2 113h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 SBOC 0
5
THCEN
0
4 THCS4 0
3 THCS3 0
2 THCS2 0
1 THCS1 0
0 THCS0 0
Bit 7 : Transmit Abort (TABT) A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Bit 6 : Send BOC (SBOC) Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TBOC register. Bit 5 : Transmit HDLC Controller Enable (THCEN) 0 = Transmit HDLC Controller is not enabled 1 = Transmit HDLC Controller is enabled Bits 4 to 0 : Transmit HDLC Channel Select (THCS0 to 4). Determines which DSO channel will carry the HDLC message if enabled.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TBSE8 0
THBSE Transmit HDLC Bit Suppress 111h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 TBSE7 0
5 TBSE6 0
4 TBSE5 0
3 TBSE4 0
2 TBSE3 0
1 TBSE2 0
0 TBSE1 0
Bit 7 : Transmit Bit 8 Suppress (TBSE8) MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Transmit Bit 7 Suppress (TBSE7) Set to one to stop this bit from being used. Bit 5 : Transmit Bit 6 Suppress (TBSE6) Set to one to stop this bit from being used. Bit 4 : Transmit Bit 5 Suppress (TBSE5) Set to one to stop this bit from being used. Bit 3 : Transmit Bit 4 Suppress (TBSE4) Set to one to stop this bit from being used. Bit 2 : Transmit Bit 3 Suppress (TBSE3) Set to one to stop this bit from being used. Bit 1 : Transmit Bit 2 Suppress (TBSE2) Set to one to stop this bit from being used. Bit 0 : Transmit Bit 1 Suppress (TBSE1) LSB of the channel. Set to one to stop this bit from being used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.14.1 Transmit HDLC FIFO Control
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
THFC Transmit HDLC FIFO Control Register 187h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 TFLWM1 0
0 TFLWM0 0
Bits 7 to 2 : Unused. Must be set = 0 for proper operation. Bits 1 to 0 : Transmit HDLC FIFO Low Watermark Select (TFLWM0 to TFLWM1) TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Transmit FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes
11.5.14.2 HDLC Status and Information TLS2 provides status information for the transmit HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are latched and some are real time bits that are not latched. This section contains register descriptions that list which bits are latched and which are real time. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status register, TLS2 has the ability to initiate a hardware interrupt via the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt Mask Register (TIM2). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
TRTS2 Transmit Real-Time Status Register 2 (HDLC) 1B1h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
Bit # 7 6 5 Name -- -- -- Default 0 0 0 All bits in this register are real time.
4 -- 0
3 TEMPTY 0
2 TFULL 0
1 TLWM 0
0 TNF 0
Bits 7 to 4: Unused. Must be set = 0 for proper operation. Bit 3 : Transmit FIFO Empty (TEMPTY) A real-time bit that is set high when the FIFO is empty. Bit 2 : Transmit FIFO Full (TFULL) A real-time bit that is set high when the FIFO is full. Bit 1 : Transmit FIFO Below Low Watermark Condition (TLWM) Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM). Bit 0 : Transmit FIFO Not Full Condition (TNF) Set when the transmit 64-byte FIFO has at least 1 byte available.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TLS2 Transmit Latched Status Register 2 (HDLC) 191h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 TFDLE 0
3 TUDR 0
2 TMEND 0
1 TLWMS 0
0 TNFS 0
All bits in this register are latched and can create interrupts.
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Transmit FDL Register Empty (TFDLE) Set when the TFDL register has shifted out all 8 bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or BOC controller circuits. Bit 3 : Transmit FIFO Underrun Event (TUDR) Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. Bit 2 : Transmit Message End Event (TMEND) Set when the transmit HDLC controller has finished sending a message. Bit 1 : Transmit FIFO Below Low Watermark Set Condition (TLWMS) Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM) (rising edge detect of TLWM). Bit 0 : Transmit FIFO Not Full Set Condition (TNFS) Set when the transmit 64-byte FIFO has at least one empty byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TIM2
Transmit Interrupt Mask Register 2
1A1h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 TFDLE 0
3 TUDR 0
2 TMEND 0
1 TLWMS 0
0 TNFS 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Transmit FDL Register Empty (TFDLE) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Transmit FIFO Underrun Event (TUDR) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Transmit Message End Event (TMEND) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Transmit FIFO Below Low Watermark Set Condition (TLWMS) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Transmit FIFO Not Full Set Condition (TNFS) 0 = interrupt masked 1 = interrupt enabled
11.5.14.3 FIFO Information The Transmit FIFO Buffer Available register indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle.
Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TFBA Transmit HDLC FIFO Buffer Available 1B3h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 TFBA6 0
5 TFBA5 0
4 TFBA4 0
3 TFBA3 0
2 TFBA2 0
1 TFBA1 0
0 TFBA0 0
Bits 0 to 6 : Transmit FIFO Bytes Available (TFBAO to TFBA6) TFBA0 is the LSB.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name:
Register Description:
Address (hex):
THF Transmit HDLC FIFO 1B4h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
Bit # Name Default
7 THD7 0
6 THD6 0
5 THD5 0
4 THD4 0
3 THD3 0
2 THD2 0
1 THD1 0
0 THD0 0
Bit 7 : Transmit HDLC Data Bit 7 (THD7) MSB of a HDLC packet data byte. Bit 6 : Transmit HDLC Data Bit 6 (THD6) Bit 5 : Transmit HDLC Data Bit 5 (THD5) Bit 4 : Transmit HDLC Data Bit 4 (THD4) Bit 3 : Transmit HDLC Data Bit 3 (THD3) Bit 2 : Transmit HDLC Data Bit 2 (THD2) Bit 1 : Transmit HDLC Data Bit 1 (THD1) Bit 0 : Transmit HDLC Data Bit 0 (THD0) LSB of a HDLC packet data byte.
11.5.15 Programmable In-Band Loop-Code Generator
This register definition is repeated here for convenience. Register Name: TCR4 Register Description: Transmit Control Register 4 Address (hex): 186h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
Bit # Name Default
7 0
6 0
5 0
4 0
3 TRAIM 0
2 TAISM 0
1 TC1 0
0 TC0 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Transmit RAI Mode (TRAIM) Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = transmit normal RAI upon activation with TCR1.0 1 = transmit RAI-CI (T1.403) upon activation with TCR1.0 Bit 2 : Transmit AIS Mode (TAISM) Determines the pattern sent when TAIS (TCR1.1) is activated. 0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1 1 = transmit AIS-CI (T1.403) upon activation with TCR1.1 Bits 1 to 0 : Transmit Code Length Definition Bits (TC0 to TC1)
TC1 0 0 1 1 TC0 0 1 0 1 LENGTH SELECTED (BITS) 5 6/3 7 16/8/4/2/1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
TCD1 Transmit Code Definition Register 1 1ACh + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bit 7 : Transmit Code Definition Bit 7 (C7) First bit of the repeating pattern. Bit 6 : Transmit Code Definition Bit 6 (C6) Bit 5 : Transmit Code Definition Bit 5 (C5) Bit 4 : Transmit Code Definition Bit 4 (C4) Bit 3 : Transmit Code Definition Bit 3 (C3) Bit 2 : Transmit Code Definition Bit 2 (C2) A Don't Care if a 5-bit length is selected. Bit 1 : Transmit Code Definition Bit 1 (C1) A Don't Care if a 5- or 6-bit length is selected. Bit 0 : Transmit Code Definition Bit 0 (C0) A Don't Care if a 5-, 6-, or 7-bit length is selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
TCD2 Transmit Code Definition Register 2 1ADh + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bits 0 to 7 : Transmit Code Definition Bit 0 to 7 (C0 to C7) A Don't Care if a 5-, 6-, or 7-bit length is selected.
11.5.16 Interfacing the T1 Tx Formatter to the BERT
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TBICR Transmit BERT Interface Control Register 18Ah + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 TBDC 0
1 TBFUS 0
0 TBEN 0
Bits 7 to 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Transmit BERT Direction Control (TBDC) 0 = Transmit Path: The BERT transmits toward the network. 1 = Backplane: The BERT transmits toward the system backplane. Bit 1 : Transmit BERT Framed/Unframed Select (TBFUS) 0 = The framer will not provide data from the F-bit position (framed) 1 = The framer will clock data from the F-bit position (unframed) Bit 0 : Transmit BERT Enable (TBEN) 0 = Transmit BERT is disabled. 1 = Transmit BERT is enabled.
Register Name: Register Description: Address (hex):
TBCS1, TBCS2, TBCS3 Transmit BERT Channel Select Registers 0D4h, 0D5h, 0D6h [+ (200h x n) : where n = 0 to 3, for Ports 1 to 4]
Setting any of the CH1 through CH24 bits in the TBCS1 through TBCS3 registers will map data from those channels to the on-board BERT. TBEN must be set to one for these registers to function. Multiple, or all channels may be selected simultaneously. These registers affect the transmit-side framer only.
(MSB) CH8 CH16 CH24
CH7 CH15 CH23
CH6 CH14 CH22
CH5 CH13 CH21
CH4 CH12 CH20
CH3 CH11 CH19
CH2 CH10 CH18
(LSB) CH1 CH9 CH17
TBCS1 TBCS2 TBCS3
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 BSE8 0
TBBS Transmit BERT Bit Suppress Register 18Bh
6 BSE7 0
5 BSE6 0
4 BSE5 0
3 BSE4 0
2 BSE3 0
1 BSE2 0
0 BSE1 0
Bit 7 : Transmit Channel Bit 8 Suppress (BSE8) MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Transmit Channel Bit 7 Suppress (BSE7) Set to one to stop this bit from being used. Bit 5 : Transmit Channel Bit 6 Suppress (BSE6) Set to one to stop this bit from being used. Bit 4 : Transmit Channel Bit 5 Suppress (BSE5) Set to one to stop this bit from being used. Bit 3 : Transmit Channel Bit 4 Suppress (BSE4) Set to one to stop this bit from being used. Bit 2 : Transmit Channel Bit 3 Suppress (BSE3) Set to one to stop this bit from being used. Bit 1 : Transmit Channel Bit 2 Suppress (BSE2) Set to one to stop this bit from being used. Bit 0 : Transmit Channel Bit 1 Suppress (BSE1) LSB of the channel. Set to one to stop this bit from being used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.5.17 T1 Transmit Synchronizer
When enabled, the DS26556 transmitter has the ability to identify the D4 or ESF frame boundary within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC register. The Transmit Latched Status 3 (TLS3) register provides a latched status bit (LOFD) to indicate that a Loss-of-Frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INT. Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the recovered frame sync pulse will be output on this signal. The recovered multiframe sync pulse will be output if enabled with TIOCR.0 (TSM = 1). Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TSYNCC Transmit Synchronizer Control Register 18Eh + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 TSEN 0
1 SYNCE 0
0 RESYNC 0
Bits 7 to 3: Unused. Must be set = 0 for proper operation. Bit 2 : Transmit Synchronizer Enable (TSEN) 0 = Transmit Synchronizer Disabled 1 = Transmit Synchronizer Enabled Bit 1 : Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 0 : Resynchronize (RESYNC) When toggled from low to high, a resynchronization of the transmit side framer is initiated. Must be cleared and set again for a subsequent resync.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TLS3 Transmit Latched Status Register 3 (Synchronizer) 192h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 LOF 0
0 LOFD 0
Bits 7 to 2 : Unused. Must be set = 0 for proper operation. Bit 1 : Loss of Frame (LOF) A real-time bit that indicates that the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bit 0 : Loss Of Frame Synchronization Detect (LOFD) This latched bit is set when the transmit synchronizer is searching for the sync pattern in the incoming data stream.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) 1A2h + (200h x n) : where n = 0 to 3, for Ports 1 to 4
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 -- 0
0 LOFD 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Loss Of Frame Synchronization Detect (LOFD) 0 = Interrupt Masked 1 = Interrupt Enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6 E1 Receive Framer Table 11-15 E1 Receive Framer Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0000-000F 0010 0011 0012 0013 0014-001F 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046 0047 0048
NAME
FUNCTION
-- RHC RHBSE RDS0SEL RSIGC -- RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 RIDR25 RIDR26 RIDR27 RIDR28 RIDR29 RIDR30 RIDR31 RIDR32 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9
Unused. Must be set = 0 for proper operation Rx HDLC Control Rx HDLC Bit Suppress Rx DS0 Monitor Select Rx Signaling Control Unused. Must be set = 0 for proper operation Rx Idle Definition 1 Rx Idle Definition 2 Rx Idle Definition 3 Rx Idle Definition 4 Rx Idle Definition 5 Rx Idle Definition 6 Rx Idle Definition 7 Rx Idle Definition 8 Rx Idle Definition 9 Rx Idle Definition 10 Rx Idle Definition 11 Rx Idle Definition 12 Rx Idle Definition 13 Rx Idle Definition 14 Rx Idle Definition 15 Rx Idle Definition 16 Rx Idle Definition 17 Rx Idle Definition 18 Rx Idle Definition 19 Rx Idle Definition 20 Rx Idle Definition 21 Rx Idle Definition 22 Rx Idle Definition 23 Rx Idle Definition 24 Rx Idle Definition 25 Rx Idle Definition 26 Rx Idle Definition 27 Rx Idle Definition 28 Rx Idle Definition 29 Rx Idle Definition 30 Rx Idle Definition 31 Rx Idle Definition 32 Rx Signaling 1 Rx Signaling 2 Rx Signaling 3 Rx Signaling 4 Rx Signaling 5 Rx Signaling 6 Rx Signaling 7 Rx Signaling 8 Rx Signaling 9
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 0058-005F 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E-007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C - 008F 0090 0091 0092 0093 0094 0095 0096 0097
NAME
FUNCTION
RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 EBCR1 EBCR2 -- RDS0M -- RRTS7 -- RAF RNAF RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 -- RMMR RCR1 RCR2 RCR3 RIOCR RGCCR ERCNT RHFC -- RBICR RBBS -- RLS1 RLS2 RLS3 RLS4 RLS5 -- -- --
Rx Signaling 10 Rx Signaling 11 Rx Signaling 12 Rx Signaling 13 Rx Signaling 14 Rx Signaling 15 Rx Signaling 16 Rx Line-Code Violation Counter 1 Rx Line-Code Violation Counter 2 Rx Path-Code Violation Counter 1 Rx Path-Code Violation Counter 2 Rx Frames Out-of-Sync Counter 1 Rx Frames Out-of-Sync Counter 2 Receive E-Bit Counter 1 Receive E-Bit Counter 2 Unused. Must be set = 0 for proper operation Rx DS0 Monitor Unused. Must be set = 0 for proper operation Receive Real-Time Status 7 Unused. Must be set = 0 for proper operation Receive Align Frame Receive Non-Align Frame Receive Si Bits for Align Frame Receive Si Bits for Non-Align Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Receive Sa7 Bits Receive Sa8 Bits Unused. Must be set = 0 for proper operation Rx Master Mode Rx Control 1 Rx Control 2 Rx Control 3 Rx I/O Configuration Rx Gapped Clock Control Rx Error Count Configuration Rx HDLC FIFO Control Unused. Must be set = 0 for proper operation Unused. Must be set = 0 for proper operation Rx BERT Interface Control Rx BERT Bit Suppress Enable Unused. Must be set = 0 for proper operation Rx Latched Status 1 Rx Latched Status 2 Rx Latched Status 3 Rx Latched Status 4 Rx Latched Status 5 (HDLC) Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. 251 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0098 0099 009A 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC-00AF 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7-00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 - 00DF
NAME
FUNCTION
RSS1 RSS2 RSS3 RSS4 -- -- -- RIIR RIM1 RIM2 RIM3 RIM4 RIM5 -- -- -- RSCSE1 RSCSE2 RSCSE3 RSCSE4 -- RRTS1 -- RRTS3 -- RRTS5 RHPBA RHF -- RCMR1 RCMR2 RCMR3 RCMR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBCS1 RBCS2 RBCS3 RBCS4 --
Rx Signaling Change-of-State Status 1 Rx Signaling Change-of-State Status 2 Rx Signaling Change-of-State Status 3 Rx Signaling Change-of-State Status 4 Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Rx Interrupt Information Reg Rx Interrupt Mask Reg 1 Rx Interrupt Mask Reg 2 Rx Interrupt Mask Reg 3 Rx Interrupt Mask Reg 4 Rx Interrupt Mask Reg 5 (HDLC) Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation Rx Signaling Change-of-State Enable 1 Rx Signaling Change-of-State Enable 2 Rx Signaling Change-of-State Enable 3 Rx Signaling Change-of-State Enable 4 Unused. Must be set = 0 for proper operation. Rx Real-Time Status 1 Unused. Must be set = 0 for proper operation. Rx Real-Time Status 3 Unused. Must be set = 0 for proper operation. Rx Real-Time Status 5 (HDLC) Rx HDLC Packet Bytes Available Rx HDLC FIFO Unused. Must be set = 0 for proper operation. Rx Channel Mark 1 Rx Channel Mark 2 Rx Channel Mark 3 Rx Channel Mark 4 Rx Signaling Insertion 1 Rx Signaling Insertion 2 Rx Signaling Insertion 3 Rx Signaling Insertion 4 Rx Gapped Clock Channel Select 1 Rx Gapped Clock Channel Select 2 Rx Gapped Clock Channel Select 3 Rx Gapped Clock Channel Select 4 Rx Channel Idle Code Enable 1 Rx Channel Idle Code Enable 2 Rx Channel Idle Code Enable 3 Rx Channel Idle Code Enable 4 Rx BERT Channel Select 1 Rx BERT Channel Select 2 Rx BERT Channel Select 3 Rx BERT Channel Select 4 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.1 E1 Receive Framer Description and Operation
Four fully independent DS1/E1 framers are included within the DS26556. Each framer can be individually programmed to accept AMI, HDB3 (E1), B8ZS (T1), or NRZ data. In E1 mode each framer supports FAS, CRC-4, and CAS frame formats, and detects/reports common alarms such as AIS, RAI, LOS, and LOF. Performance monitor counters are maintains for each port which report bipolar/line code violations, CRC-4 errors, FAS errors, and E-bits. Each framer has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode) and includes 64 byte FIFO buffers in both the transmit and receive paths. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin. Additional details concerning the operation of the E1 framer are included within the register descriptions within this section.
11.6.2 Receive Master Mode Register
The Receive Master Mode Register (RMMR) controls the initialization of the receive side framer. The FRM_EN bit may be left `low' if the framer for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Address (hex): Bit # Name Default 7 FRM_EN 0
RMMR Receive Master Mode Register 0080, 0280, 0480, 0680
6 INIT_DONE 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 SFTRST 0
0 T1/E1 0
Bit 7 : Framer Enable (FRM_EN) This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled - held in low power state 1 = Framer enabled - all features active Bit 6 : Initialization Done (INIT_DONE) The host (user) must set this bit once he/she has written the configuration registers. The host is required to write or clear all RAM based registers (addresses 00H to 7FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bits 5 to 2 : Unused. Must be set = 0 for proper operation. Bit 1 : Soft Reset (SFTRST) Level sensitive processor reset. Should be taken high then low to reset and initialize the internal processor. 0 = Normal operation 1 = Hold the internal RISC in reset. This bit only affects the receive side processor. Bit 0 : Receiver T1/E1 Mode Select (T1/E1) Sets operating mode for receiver only! This bit must be set to the desired state before writing INIT_DONE. 0 = T1 operation 1 = E1 operation
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.3 Interrupt Information Registers
The Interrupt Information Registers provide an indication of which DS26556 Status Registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the 6 E1 receive status registers are causing the interrupt. The Interrupt Information Register bits will clear once the appropriate interrupt has been serviced and cleared, as long as no other interrupt condition is present in the associated status register. Status bits that have been masked via the Receive Interrupt Mask (RIMx) registers, will also be masked from the IIR registers. Register Name: Register Description: Address (hex): Bit # Name Default 7 0
RIIR Receive Interrupt Information Register 009F, 029F, 049F, 069F
6 0
5 RLS6 0
4 RLS5 0
3 RLS4 0
2 RLS3 0
1 RLS2 0
0 RLS1 0
11.6.4 E1 Receive Control Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RCR1 Receive Control Register 1 0081, 0281, 0481, 0681
6 RHDB3 0
5 RSIGM 0
4 RG802 0
3 RCRC4 0
2 FRC 0
1 SYNCE 0
0 RESYNC 0
Bit 7 : Unused. Must be set = 0 for proper operation. Bit 6 : Receive HDB3 Enable (RHDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 5 : Receive Signaling Mode Select (RSIGM) 0 = CAS signaling mode 1 = CCS signaling mode Bit 4 : Receive G.802 Enable (RG802) 0 = do not force RCHMRK high during bit 1 of time slot 26 1 = force RCHMRK high during bit 1 of time slot 26 Bit 3 : Receive CRC4 Enable (RCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 2 : Frame Resync Criteria (FRC) 0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Bit 1 : Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 0 : Resynchronize (RESYNC) When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 11-2 E1 Sync/Resync Criteria
FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA Three consecutive incorrect FAS received Alternate: (RCR1.2 = 1) The above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error or for a period of 1 multiframe, all the bits in time slot 16 are zero. Alternate: (RSIGC.4 = 1) The above criteria are met or 1 multiframe is received with all bits in time slot 16 set to 0. G.706 4.1.1 and 4.1.2 ITU SPEC.
FAS
FAS present in frame N and N + 2, and FAS not present in frame N + 1
CRC4
Two valid MF alignment words found within 8 ms Valid MF alignment word found.
G.706 4.2 and 4.3.2
CAS
Alternate: (RSIGC.4 = 1) Valid MF alignment word found and previous time slot 16 contains code other than all zeros.
G.732 5.2
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RCR2 Receive Control Register 2 0082, 0282, 0482, 0682
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 -- 0
0 RLOSA 0
Bits 7 to 1: Unused. Must be set = 0 for proper operation. Bit 0 : Receive Loss of Signal Alternate Criteria (RLOSA) Defines the criteria for an LOS condition. 0 = LOS declared upon 255 consecutive zeros (125ms) 1 = LOS declared upon 2048 consecutive zeros (1ms)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 IDF 0
RCR3 Receive Control Register 3 0083, 0283, 0483, 0683
6
--
0
5 RSERC 0
4 -- 0
3 -- 0
2 RLB 0
1 PLB 0
0 FLB 0
Bit 7 : Input Data Format (IDF) 0 = Bipolar data is expected at RPOS and RNEG (either AMI or B8ZS) 1 = NRZ data is expected at RPOS. The BPV counter will be disabled and RNEG will be ignored by the DS26556. Bit 6 : Unused. Must be set = 0 for proper operation. Bit 5 : RSER Control (RSERC) 0 = allow RSER to output data as received under all conditions (normal operation) 1 = force RSER to one under loss of frame alignment conditions Bits 4 & 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Remote Loopback (RLB) 0 = loopback disabled 1 = loopback enabled Bit 1 : Payload Loopback (PLB) 0 = loopback disabled 1 = loopback enabled
When PLB is enabled, the following will occur: 1) 2) 3) 4) Data will be transmitted at the TTIP and TRING pins synchronous with RCLK instead of TCLK All of the receive side signals will continue to operate normally The TCHMKR signal is forced low Data at the TDATAI pin is ignored Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the DS26556 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS26556. In this loopback, data input via the RTIP and RRING pins will be transmitted back to the TTIP and TRING pins. Data will continue to pass through the receive side framer of the DS26556 as it would normally and the data from the transmit side formatter will be ignored.
Bit 0 : Framer Loopback (FLB) 0 = loopback disabled 1 = loopback enabled
This loopback is useful in testing and debugging applications. In FLB, the DS26556 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1) (T1 mode) an unframed all one's code will be transmitted at TTIP and TRING (E1 mode) normal data will be transmitted at TTIP and TRING 2) Data at RPOS and RNEG will be ignored 3) All receive side signals will take on timing synchronous with TCLK instead of RCLK. Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition. 256 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RCLKINV 0
RIOCR Receive I/O Configuration Register 0084, 0284, 0484, 0684
6 RSYNCINV 0
5 H100EN 0
4 HSCLKM 0
3 -- 0
2 0
1 RSMS2 0
0 RSMS1 0
Bit 7 : RCLK Invert (RCLKINV) 0 = No inversion 1 = Invert RCLK input Bit 6 : RSYNC Invert (RSYNCINV) 0 = No inversion 1 = Invert RSYNC as either input or output Bit 5 : H.100 SYNC Mode (H100EN). See Section 8.6.1. 0 = Normal operation 1 = HSSYNC shifted Bit 4 : HSYSCLK Mode Select (RSCLKM) 0 = if HSYSCLK is 1.544MHz 1 = if HSYSCLK is 2.048MHz Bits 3 & 2 : Unused. Must be set = 0 for proper operation. Bit 1 : RSYNC Mode Select 2 (RSMS2) T1: RSYNC pin must be programmed in the output frame mode 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames E1: RSYNC pin must be programmed in the output multiframe mode 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries Bit 0 : RSYNC Mode Select 1 (RSMS1) Selects frame or multiframe pulse at RSYNC pin. 0 = frame mode 1 = multiframe mode
11.6.5 E1 Receive Status and Information
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INT signal.
Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the internal status signals can be read at any time from the real time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a change-of-state for an alarm, condition, or event; and operate in a read-then-write fashion. The user should read the value of the desired status bit, and then write a 1 to that particular bit location in
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver order to clear the latched value (write a 0 to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again.
Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (RIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs. The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin will clear even if the alarm is still present.
Note that some conditions may have multiple status indications. For example, Receive Loss of Frame (RLOF) provides the following indications: Real-time indication that the receiver is not synchronized with incoming data stream. Read-only bit that remains high as long as the condition is present. Latched indication that the receiver has loss synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (rising edge detect of RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (falling edge detect of RRTS1.0).
RRTS1.0 (RLOF)
RLS1.0 (RLOFD)
RLS1.4 (RLOFC)
Table 11-16 E1 Alarm Criteria
ALARM RLOF SET CRITERIA An RLOF condition exist on power up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated via RCR1.0 255 or 2048 consecutive zeros received as determined by RCR2.0 Bit 3 of non-align frame set to one for three consecutive occasions In 255-bit times, at least 32 ones are received Bit 3 of non-align frame set to zero for three consecutive occasions More than two zeros in two frames (512 bits) G.775/G.962 CLEAR CRITERIA ITU SPEC.
RLOS
RRAI
O.162
RAIS
Fewer than three zeros in two frames (512 bits)
O.162
RDMA
Bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes
V52LNK
2 out of 3 Sa7 bits are zero
G.965
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RRTS1 Receive Real-Time Status Register 1 00B0, 02B0, 04B0, 06B0
6 -- 0
5 -- 0
4 -- 0
3 RRAI 0
2 RAIS 0
1 RLOS 0
0 RLOF 0
All bits in this register are real-time (not latched).
Bits 7 to 4 : Unused. Must be set = 0 for proper operation Bit 3 : Receive Remote Alarm Indication Condition (RRAI) Set when a remote alarm is received at RPOS and RNEG. Bit 2 : Receive Alarm Indication Signal Condition (RAIS) Set when an unframed all one's code is received at RPOS and RNEG. Bit 1 : Receive Loss of Signal Condition (RLOS) Set when 255 (or 2048 if RCR2.0 = 1) consecutive zeros have been detected at RPOS and RNEG. Bit 0 : Receive Loss of Frame Condition (RLOF) Set when the DS26556 is not synchronized to the received data stream.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RRAIC 0
RLS1 Receive Latched Status Register 1 0090, 0290, 0490, 0690
6 RAISC 0
5 RLOSC 0
4 RLOFC 0
3 RRAID 0
2 RAISD 0
1 RLOSD 0
0 RLOFD 0
All bits in this register are latched and can create interrupts.
Bit 7 : Receive Remote Alarm Condition Clear (RRAIC) Change of state indication. Set when a RRAI condition has cleared (falling edge detect of RRAI). Bit 6 : Receive AIS Condition Clear (RAISC) Change of state indication. Set when a RAIS condition has cleared (falling edge detect of RAIS). Bit 5 : Receive Loss of Signal Condition Clear (RLOSC) Change of state indication. Set when an RLOS condition has cleared (falling edge detect of RLOS). Bit 4 : Receive Loss of Frame Condition Clear (RLOFC) Change of state indication. Set when an RLOF condition has cleared (falling edge detect of RLOF). Bit 3 : Receive Remote Alarm Condition Detect (RRAID) Change of state indication. Set when a remote alarm is received at RPOS and RNEG (rising edge detect of RRAI). Bit 2 : Receive AIS Condition Detect (RAISD) Change of state indication. Set when an unframed all one's code is received at RPOS and RNEG (rising edge detect of RAIS). Bit 1 : Receive Loss of Signal Condition Detect (RLOSD) Change of state indication. Set when 255 (or 2048 if RCR2.0 = 1) consecutive zeros have been detected at RPOS and RNEG (rising edge detect of RLOS). Bit 0 : Receive Loss of Frame Condition Detect (RLOFD) Change of state indication that the DS26556 has lost synchronized to the received data stream (rising edge detect of RLOF).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RRAIC 0
RIM1 Receive Interrupt Mask Register 1 00A0, 02A0, 04A0, 06A0
6 RAISC 0
5 RLOSC 0
4 RLOFC 0
3 RRAID 0
2 RAISD 0
1 RLOSD 0
0 RLOFD 0
Bit 7 : Receive Remote Alarm Clear (RRAIC) 0 = interrupt masked 1 = interrupt enabled Bit 6 : Receive AIS Clear (RAISC) 0 = interrupt masked 1 = interrupt enabled Bit 5 : Receive Loss of Signal Clear (RLOSC) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive Loss of Frame Clear (RLOFC) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive Remote Alarm Detect (RRAID) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive AIS Detect (RAISD) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive Loss of Signal Detect (RLOSD) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Loss of Frame Detect (RLOFD) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RLS2 Receive Latched Status Register 2 0091, 0291, 0491, 0691
6 CRCRC 0
5 CASRC 0
4 FASRC 0
3 RSA1 0
2 RSA0 0
1 RCMF 0
0 RAF 0
All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register.
Bit 7 : Unused. Must be set = 0 for proper operation. Bit 6 : CRC Resync Criteria Met Event (CRCRC) Set when 915/1000 codewords are received in error. Bit 5 : CAS Resync Criteria Met Event (CASRC) Set when 2 consecutive CAS MF alignment words are received in error. Bit 4 : FAS Resync Criteria Met Event (FASRC) Set when 3 consecutive FAS words are received in error. Bit 3 : Receive Signaling All Ones Event (RSA1) Set when the contents of time slot 16 contain less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 2 : Receive Signaling All Zeros Event (RSA0) Set when over a full MF, time slot 16 contains all zeros. Bit 1 : Receive CRC4 Multiframe Event (RCMF) Set on CRC4 multiframe boundaries; will continue to be set every 2ms on an arbitrary boundary if CRC4 is disabled. Bit 0 : Receive Align Frame Event (RAF) Set every 250ms at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RIM2 Receive Interrupt Mask Register 2 00A1, 02A1, 04A1, 06A1
6 -- 0
5 -- 0
4 -- 0
3 RSA1 0
2 RSA0 0
1 RCMF 0
0 RAF 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Receive Signaling All Ones Event (RSA1) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive Signaling All Zeros Event (RSA0) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive CRC4 Multiframe Event (RCMF) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Align Frame Event (RAF) 0 = interrupt masked 1 = interrupt enabled
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RRTS3 Receive Real-Time Status Register 3 00B2, 02B2, 04B2, 06B2
6 -- 0
5 -- 0
4 -- 0
3 LORC 0
2 -- 0
1 V52LNK 0
0 RDMA 0
All bits in this register are real-time (not latched).
Bits 7 to 4 : Unused. Bit 3 : Loss of Receive Clock Condition (LORC) Set when the RCLK pin has not transitioned for one channel time. Bit 2 : Unused. Bit 1 : V5.2 Link Detected Condition (V52LNK) Set on detection of a V5.2 link identification signal. (G.965). Bit 0 : Receive Distant MF Alarm Condition (RDMA) Set when bit-6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RLS3 Receive Latched Status Register 3 0092, 0292, 0492, 0692
Bit # 7 6 5 4 3 Name LORCC -- V52LNKC RDMAC LORCD Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
2 -- 0
1 V52LNKD 0
0 RDMAD 0
Bit 7 : Loss of Receive Clock Clear (LORCC) Change of state indication. Set when a LORC condition has cleared (falling edge detect of LORC). Bits 6 : Unused .
Bit 5 : V5.2 Link Detected Clear (V52LNKC) Change of state indication. Set when a V52LNK condition has cleared (falling edge detect of V52LNK). Bit 4 : Receive Distant MF Alarm Clear (RDMAC) Change of state indication. Set when a RDMA condition has cleared (falling edge detect of RDMA). Bit 3 : Loss of Receive Clock Detect (LORCD) Change of state indication. Set when the RCLK pin has not transitioned for one channel time (rising edge detect of LORC). Bits 2 : Unused. Bit 1 : V5.2 Link Detect (V52LNKD) Change of state indication. Set on detection of a V5.2 link identification signal. (G.965). This is the rising edge detect of V52LNK. Bit 0 : Receive Distant MF Alarm Detect (RDMAD) Change of state indication. Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is the rising edge detect of RDMA.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 LORCC 0
RIM3 Receive Interrupt Mask Register 3 00A2, 02A2, 04A2, 06A2
6 -- 0
5 V52LNKC 0
4 RDMAC 0
3 LORCD 0
2 -- 0
1 V52LNKD 0
0 RDMAD 0
Bit 7 : Loss of Receive Clock Clear (LORCC) 0 = interrupt masked 1 = interrupt enabled Bits 6 : Unused. Must be set = 0 for proper operation. Bit 5 : V5.2 Link Detected Clear (V52LNKC) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive Distant MF Alarm Clear (RDMAC) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Loss of Receive Clock Detect (LORCD) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Unused. Must be set = 0 for proper operation. Bit 1 : V5.2 Link Detect (V52LNKD) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Distant MF Alarm Detect (RDMAD) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CSC5 0
RRTS7 Receive Real-Time Status Register 7 0062, 0262, 0462, 0662
6 CSC4 0
5 CSC3 0
4 CSC2 0
3 CSC0 0
2 CRC4SA 0
1 CASSA 0
0 FASSA 0
All bits in this register are real-time (not latched).
Bits 7 to 3 : CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC4) The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter rolls over. CSC0 is the LSB of the 6-bit counter. (Note: The next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.) Bit 2 : CRC4 MF Sync Active (CRC4SA) Set while the synchronizer is searching for the CRC4 MF alignment word. Bit 1 : CAS MF Sync Active (CASSA) Set while the synchronizer is searching for the CAS MF alignment word. Bit 0 : FAS Sync Active (FASSA) Set while the synchronizer is searching for alignment at the FAS level.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
RLS4 Receive Latched Status Register 4 0093, 0293, 0493, 0693
6 0
5 0
4 0
3 RSCOS 0
2 1SEC 0
1 TIMER 0
0 RMF 0
All bits in this register are latched. There is no associated real-time register.
Bits 7 to 4 : Unused Bit 3 : Receive Signaling Change Of State Event (RSCOS) Set when any channel selected by the Receive Signaling Change Of State Interrupt Enable registers (RSCSE1 through RSCSE3), changes signaling state. Bit 2 : One-Second Timer (1SEC) Set on every one-second interval based on RCLK. Bit 1 : Timer Event (TIMER) Follows the error counter update interval as determined by the ECUS bit in the Error Counter Configuration Register (ERCNT). T1: Set on increments of 1 second or 42ms based on RCLK. E1: Set on increments of 1 second or 62.5ms based on RCLK. Bit 0 : Receive Multiframe Event (RMF) Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
RIM4 Receive Interrupt Mask Register 4 00A3, 02A3, 04A3, 06A3
6 0
5 0
4 0
3 RSCOS 0
2 1SEC 0
1 TIMER 0
0 RMF 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Receive Signaling Change Of State Event (RSCOS) 0 = interrupt masked 1 = interrupt enabled Bit 2 : One-Second Timer (1SEC) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Timer Event (TIMER) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.6 E1 Error Count Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 1SECS 0
ERCNT Error Counter Configuration Register 0086, 0286, 0486, 0686
6 MCUS 0
5 MECU 0
4 ECUS 0
3 EAMS 0
2 -- 0
1 -- 0
0 LCVCRF 0
Bit 7 : One-Second Select (1SECS) When timed update is enabled by EAMS, setting this bit for a specific framer will allow that framer's counters to latch on the one-second reference from framer #1. Note that this bit should always be clear for framer #1. 0 = Use internally generated one-second timer. 1 = Use 1 second timer from framer #1. Bit 6 : Manual Counter Update Select (MCUS) When manual update mode is enabled with EAMS, this bit can be used to allow the GLCE bit in GCR1 to latch all counters. Useful for synchronously latching counters of multiple framers. 0 = MECU is used to manually latch counters. 1 = GLCE is used to manually latch counters. Bit 5 : Manual Error Counter Update (MECU) When enabled by ERCNT.3, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 250ms before reading the error count registers to allow for proper update. Bit 4 : Error Counter Update Select (ECUS) T1 mode: 0 = Update error counters once a second 1 = Update error counters every 42ms (336 frames) E1 mode: 0 = Update error counters once a second 1 = Update error counters every 62.5ms (500 frames) Bit 3 : Error Accumulation Mode Select (EAMS) 0 = ERCNT.4 determines accumulation time (timed update) 1 = ERCNT.5 determines accumulation time (manual update) Bits 2 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : E1 Line Code Violation Count Register Function Select (LCVCRF) 0 = do not count excessive zeros 1 = count excessive zeros
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.6.1 E1 Line Code Violation Count Register (LCVCR) Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side, HDB3 codewords are not counted as BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** - 2 before the VCR would saturate. See Table 11-17.
Table 11-17 E1 Line Code Violation Counting Options
E1 CODE VIOLATION SELECT (ERCNT.0) 0 1 WHAT IS COUNTED IN THE LCVCRs BPVs CVs
Register Name: Register Description: Address (hex): Bit # Name Default 7 LCVC15 0
LCVCR1 Line Code Violation Count Register 1 0050, 0250, 0450, 0650
6 LCVC14 0
5 LCVC13 0
4 LCVC12 0
3 LCVC11 0
2 LCVC10 0
1 LCVC9 0
0 LCCV8 0
Bits 7 to 0 : Line Code Violation Counter Bits 15 to 8 (LCVC15 to LCVC8). LCV15 is the MSB of the 16-bit code violation count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 LCVC7 0
LCVCR2 Line Code Violation Count Register 2 0051, 0251, 0451, 0651
6 LCVC6 0
5 LCVC5 0
4 LCVC4 0
3 LCVC3 0
2 LCVC2 0
1 LCVC1 0
0 LCVC0 0
Bits 7 to 0 : Line Code Violation Counter Bits 7 to 0 (LCVC7 to LCVC0) LCV0 is the LSB of the 16-bit code violation count. 11.6.6.2 E1 Path Code Violation Count Register (PCVCR) In E1 operation, the Path Code Violation Count register records CRC4 errors. Since the maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
The Path Code Violation Count Register 1 (PCVCR1) is the most significant word and PCVCR2 is the least significant word of a 16-bit counter that records path violations (PVs).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 PCVC15 0
PCVCR1 Path Code Violation Count Register 1 0052, 0252, 0452, 0652
6 PCVC14 0
5 PCVC13 0
4 PCVC12 0
3 PCVC11 0
2 PCVC10 0
1 PCVC9 0
0 PCVC8 0
Bits 7 to 0 : Path Code Violation Counter Bits 15 to 8 (PCVC15 to PCVC8) PCVC15 is the MSB of the 16-bit path code violation count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 PCVC7 0
PCVCR2 Path Code Violation Count Register 2 0053, 0253, 0453, 0653
6 PCVC6 0
5 PCVC5 0
4 PCVC4 0
3 PCVC3 0
2 PCVC2 0
1 PCVC1 0
0 PCVC0 0
Bits 7 to 0 : Path Code Violation Counter Bits 7 to 0 (PCVC7 to PCVC0) PCVC0 is the LSB of the 16-bit path code violation count. 11.6.6.3 E1 Frames Out-of-Sync Count Register (FOSCR) In E1 mode, the FOSCR counts word errors in the Frame Alignment Signal in time slot 0. This counter is disabled when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a onesecond period is 4000, this counter cannot saturate.
The Frames Out of Sync Count Register 1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16-bit counter that records frames out of sync. Register Name: Register Description: Address (hex): Bit # Name Default 7 FOS15 0
FOSCR1 Frames Out Of Sync Count Register 1 0054, 0254, 0454, 0654
6 FOS14 0
5 FOS13 0
4 FOS12 0
3 FOS11 0
2 FOS10 0
1 FOS9 0
0 FOS8 0
Bits 7 to 0 : Frames Out of Sync Counter Bits 15 to 8 (FOS15 to FOS8) FOS15 is the MSB of the 16-bit frames out of sync count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 FOS7 0
FOSCR2 Frames Out Of Sync Count Register 2 0055, 0255, 0455, 0655
6 FOS6 0
5 FOS5 0
4 FOS4 0
3 FOS3 0
2 FOS2 0
1 FOS1 0
0 FOS0 0
Bits 7 to 0 : Frames Out of Sync Counter Bits 7 to 0 (FOS7 to FOS0) FOS0 is the LSB of the 16-bit frames out of sync count.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.6.4 E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
Register Name: Register Description: Address (hex): Bit # Name Default 7 EB15 0
EBCR1 E-Bit Count Register 1 0056, 0256, 0456, 0656
6 EB14 0
5 EB13 0
4 EB12 0
3 EB11 0
2 EB10 0
1 EB9 0
0 EB8 0
Bits 7 to 0 : E-Bit Counter Bits 15 to 8 (EB15 to EB8) EB15 is the MSB of the 16-bit E-Bit count.
Register Name: Register Description: Address (hex): Bit # Name Default 7 EB7 0
EBCR2 E-Bit Count Register 2 0057, 0257, 0457, 0657
6 EB6 0
5 EB5 0
4 EB4 0
3 EB3 0
2 EB2 0
1 EB1 0
0 EB0 0
Bits 7 to 0 : E-Bit Counter Bits 7 to 0 (EB7 to EB0) EB0 is the LSB of the 16-bit E-Bit count.
11.6.7 DS0 Monitoring Function
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RDS0SEL Receive Channel Monitor Select 0012, 0212, 0412, 0612
6 -- 0
5 -- 0
4 RCM4 0
3 RCM3 0
2 RCM2 0
1 RCM1 0
0 RCM0 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bits 4 to 0 : Receive Channel Monitor Bits (RCM4 to RCM0) RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data will appear in the RDS0M register.
Register Name: Register Description: Address (hex): Bit # Name Default 7 B1 0
RDS0M Receive DS0 Monitor Register 0060, 0260, 0460, 0660
6 B2 0
5 B3 0
4 B4 0
3 B5 0
2 B6 0
1 B7 0
0 B8 0
Bits 7 to 0 : Receive DS0 Channel Bits (B1 to B8) Receive channel data that has been selected by the Receive Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be received).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.8 E1 Receive Signaling Operation
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RSIGC Receive Signaling Control Register 0013, 0213, 0413, 0613
6 -- 0
5 -- 0
4 CASMS 0
3 -- 0
2 0
1 0
0 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : CAS Mode Select (CASMS) 0 = The DS26556 will initiate a resync when two consecutive multiframe alignment signals have been received with an error. 1 = The DS26556 will initiate a resync when two consecutive multiframe alignment signals have been received with an error, or 1 multiframe has been received with all the bits in time slot 16 in state 0. Alignment criteria are met when at least one bit in state 1 is present in the time slot
16 preceding the multiframe alignment signal first detected (G.732 alternate criteria).
Bit 3 to 0 : Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RS1 to RS16 Receive Signaling Registers 0040 to 004F, 0240 to 024F, 0440 to 044F, 0640 to 064F
The Receive Signaling Registers are frozen and not updated during a loss of sync condition. They contain the most recent signaling information before the LOF occurred.
(MSB) 0 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH13-A CH14-A CH15-A
0 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH13-B CH14-B CH15-B
0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C
0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D
X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A
Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B
X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C
(LSB) X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D
RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16
Register Name: Register Description: Address (hex):
RSS1, RSS2, RSS3, RSS4 Receive Signaling Status Registers 0098 to 009B, 0298 to 029B, 0498 to 049B, 0698 to 069B
When a channel's signaling data changes state, the respective bit in registers RSS1-RSS4 will be set and latched. The RSCOS bit (RLSR4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1-4. The INT signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read. Note that in CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3 represents reserved bits and the distant multiframe alarm.
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1* CH9 CH17* CH25
RSS1 RSS2 RSS3 RSS4
Status bits in this register are latched.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive Signaling Change of State Enable 00A8 to 00AB, 02A8 to 02AB, 04A8 to 04AB, 06A8 to 06AB
Setting any of the CH1 through CH32 bits in the RSCSE1 through RSCSE4 registers cause RSCOS (RLSR4.3) to be set when that channel's signaling data changes state.
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1* CH9 CH17* CH25
RSCSE1 RSCSE2 RSCSE3 RSCSE4
Register Name: Register Description: Address (hex):
RSI1, RSI2, RSI3, RSI4 Receive Signaling Reinsertion Enable Registers 00C8 to 00CB, 02C8 to 02CB, 04C8 to 04CB, 06C8 to 06CB
Setting any of the CH1 through CH32 bits in the RSI1 through RSI4 registers cause signaling data to be reinserted for the associated channel.
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1 CH9 CH17 CH25
RSI1 RSI2 RSI3 RSI4
11.6.9 E1 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Thirtytwo Receive Idle Definition Registers (RIDR1-RIDR32) are provided to set the 8-bit idle code for each channel. The Receive Channel Idle Code Enable registers (RCICE1-4) are used to enable idle code replacement on a per channel basis. Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
RIDR1 to RIDR32 Receive Idle Code Definition Registers 1 to 32 0020 to 003F, 0220 to 023F, 0420 to 043F, 0620 to 063F
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bits 7 to 0 : Per-Channel Idle Code Bits (C0 to C7) C0 is the LSB of the Code (this bit is transmitted last). Address 20H is for channel 1, address 3FH is for channel 32.
The Receive Channel Idle Code Enable Registers (RCICE1/2/3/4) are used to determine which of the 32 E1 channels from the E1 line to the backplane should be overwritten with the code placed in the Receive Idle Code Definition Register. Register Name: Register Description: Address (hex):
RCICE1, RCICE2, RCICE3, RCICE4 Receive Channel Idle Code Enable Registers 00D0 to 00D3, 02D0 to 02D3, 04D0 to 04D3, 06D0 to 06D3
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1 CH9 CH17 CH25
RCICE1 RCICE2 RCICE3 RCICE4
Bits 7 to 0 : Receive Channels 1 to 32 Code Insertion Control Bits (CH1 to CH32) 0 = do not insert data from the Idle Code Array into the receive data stream 1 = insert data from the Idle Code Array into the receive data stream
11.6.10 E1 Receive Channel Mark Registers
The Receive Channel Mark Registers (RCMR1/RCMR2/RCMR3/RCMR4) control the mapping of channels to the cell/packet interface and the RCHMRK pin. The RCHMRK signal is internally used to select which channels will be mapped to the cell/packet interface. Externally, the signal can be used to multiplex TDM data into channels not used by the cell/packet interface. When the appropriate bits are set to 1, the cell/packet function is mapped to that channel and externally the RCHMRK pin is held high during the entire corresponding channel time. Register Name: Register Description: Address (hex):
(MSB) CH8 CH16 CH24 CH32 RCMR1, RCMR2, RCMR3, RCMR4 Receive-Channel Mark Registers 00C4 to 00C7, 02C4 to 02C7, 04C4 to 04C7, 06C4 to 06C7 (LSB) CH1 CH9 CH17 CH25/Fbit
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
RCMR1 RCMR2 RCMR3 RCMR4*
Bits 7 to 0 : Receive Channels 32 to 1 Channel Mark Control Bits (CH1 to CH32) 0 = force the RCHMRK pin to remain low during this channel time 1 = force the RCHMRK pin high during this channel time
In T1 mode, the LSB of RCMR4 determines whether or not the RCHMRK signal pulses high during the F-bit time: RCMR4.0 = 0, do not pulse RCHMRK during the F-bit RCMR4.0 = 1, pulse RCHMRK during the F-bit In this mode RCMR4.1 to RCMR4.7 should be set to 0.
11.6.11 Fractional E1 Support (Gapped Clock Mode)
Register Name: Register Description: Address (hex):
RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive Gapped Clock Channel Select Registers 00CC to 00CF, 02CC to 02CF, 04CC to 04CF, 06CC to 06CF
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1 CH9 CH17 CH25
RGCCS1 RGCCS2 RGCCS3 RGCCS4
Bits 7 to 0 : Receive Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32) 0 = no clock is present on RCHMRK during this channel time 1 = force a clock on RCHMRK during this channel time. The clock will be synchronous with RCLK. Register Name: RGCCR Register Description: Receive Gapped Clock Control Register Address (hex): 0085, 0285, 0485, 0685
Bit # Name Default
7 RCCF 0
6 RGCE 0
5 0
4 0
3 0
2 0
1 0
0 0
Bit 7 : Receive Channel Clock Format (RCCF) This bit controls the function of the RCHMRK pin went it is in the channel clock mode and the RGCCR.6 bit is set = 1. Channel clock mode is enabled in the RCHMRK Pin Function Select (RPFS) register. 0 = 64kbps, clock output during all 8 bits 1 = 56kbps, clock output during 7 MSBs Bit 6 :/ Receive Gapped Clock Enable (RGCE) This bit controls the function of the RCHMRK pin went it is in the channel clock mode. Channel clock mode is enabled in the RCHMRK Pin Function Select (RPFS) register. 0 = RCHMRK outputs a pulse during the LSB of each channel time. 1 = RCHMRK outputs a gapped bit clock as selected by the RGCCS1 through RGCCC4 registers. Bits 5 to 0 : Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.12 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode)
Register Name: Register Description: Address (hex): Bit # Name Default 7 Si 0
RAF Receive Align Frame Register 0064, 0264, 0464, 0664
6 0 0
5 0 0
4 1 0
3 1 0
2 0 0
1 1 0
0 1 0
Bit 7 : International Bit (Si) Bit 6 : Frame Alignment Signal Bit (0) Bit 5 : Frame Alignment Signal Bit (0) Bit 4 : Frame Alignment Signal Bit (1) Bit 3 : Frame Alignment Signal Bit (1) Bit 2 : Frame Alignment Signal Bit (0) Bit 1 : Frame Alignment Signal Bit (1) Bit 0 : Frame Alignment Signal Bit (1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 Si 0
RNAF Receive Non-Align Frame Register 0065, 0256, 0456, 0665
6 1 0
5 A 0
4 Sa4 0
3 Sa5 0
2 Sa6 0
1 Sa7 0
0 Sa8 0
Bit 7 : International Bit (Si) Bit 6 : Frame Non-Alignment Signal Bit (1) Bit 5 : Remote Alarm (A) Bit 4 : Additional Bit 4 (Sa4) Bit 3 : Additional Bit 5 (Sa5) Bit 2 : Additional Bit 6 (Sa6) Bit 1 : Additional Bit 7 (Sa7) Bit 0 : Additional Bit 8 (Sa8)
Register Name: Register Description: Address (hex): Bit # Name Default 7 SiF14 0
RsiAF Received Si Bits of the Align Frame 0066, 0266, 0466, 0666
6 SiF12 0
5 SiF10 0
4 SiF8 0
3 SiF6 0
2 SiF4 0
1 SiF2 0
0 SiF0 0
Bit 0 : Si Bit of Frame 0 (SiF0) Bit 1 : Si Bit of Frame 2 (SiF2) Bit 2 : Si Bit of Frame 4 (SiF4) Bit 3 : Si Bit of Frame 6 (SiF6) Bit 4 : Si Bit of Frame 8 (SiF8) Bit 5 : Si Bit of Frame 10 (SiF10) Bit 6 : Si Bit of Frame 12 (SiF12) Bit 7 : Si Bit of Frame 14 (SiF14)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 SiF15 0
RSiNAF Received Si Bits of the Non-Align Frame 0067, 0267, 0467, 0667
6 SiF13 0
5 SiF11 0
4 SiF9 0
3 SiF7 0
2 SiF5 0
1 SiF3 0
0 SiF1 0
Bit 7 : Si Bit of Frame 15 (SiF15) Bit 6 : Si Bit of Frame 13 (SiF13) Bit 5 : Si Bit of Frame 11 (SiF11) Bit 4 : Si Bit of Frame 9 (SiF9) Bit 3 : Si Bit of Frame 7 (SiF7) Bit 2 : Si Bit of Frame 5 (SiF5) Bit 1 : Si Bit of Frame 3 (SiF3) Bit 0 : Si Bit of Frame 1 (SiF1)
Register Name: Register Description: Address (hex): Bit # Name Default 7 RRAF15 0
RRA Received Remote Alarm 0068, 0268, 0468, 0668
6 RRAF13 0
5 RRAF11 0
4 RRAF9 0
3 RRAF7 0
2 RRAF5 0
1 RRAF3 0
0 RRAF1 0
Bit 7 : Remote Alarm Bit of Frame 15 (RRAF15) Bit 6 : Remote Alarm Bit of Frame 13 (RRAF13) Bit 5 : Remote Alarm Bit of Frame 11 (RRAF11) Bit 4 : Remote Alarm Bit of Frame 9 (RRAF9) Bit 3 : Remote Alarm Bit of Frame 7 (RRAF7) Bit 2 : Remote Alarm Bit of Frame 5 (RRAF5) Bit 1 : Remote Alarm Bit of Frame 3 (RRAF3) Bit 0 : Remote Alarm Bit of Frame 1 (RRAF1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RSa4F15 0
RSa4 Received Sa4 Bits 0069, 0269, 0469, 0669
6 RSa4F13 0
5 RSa4F11 0
4 RSa4F9 0
3 RSa4F7 0
2 RSa4F5 0
1 RSa4F3 0
0 RSa4F1 0
Bit 7 : Sa4 Bit of Frame 15 (RSa4F15) Bit 6 : Sa4 Bit of Frame 13 (RSa4F13) Bit 5 : Sa4 Bit of Frame 11 (RSa4F11) Bit 4 : Sa4 Bit of Frame 9 (RSa4F9) Bit 3 : Sa4 Bit of Frame 7 (RSa4F7) Bit 2 : Sa4 Bit of Frame 5 (RSa4F5) Bit 1 : Sa4 Bit of Frame 3 (RSa4F3) Bit 0 : Sa4 Bit of Frame 1 (RSa4F1)
Register Name: Register Description: Address (hex): Bit # Name Default 7 RSa5F15 0
RSa5 Received Sa5 Bits 006A, 026A, 046A, 066A
6 RSa5F13 0
5 RSa5F11 0
4 RSa5F9 0
3 RSa5F7 0
2 RSa5F5 0
1 RSa5F3 0
0 RSa5F1 0
Bit 7 : Sa5 Bit of Frame 15 (RSa5F15) Bit 6 : Sa5 Bit of Frame 13 (RSa5F13) Bit 5 : Sa5 Bit of Frame 11 (RSa5F11) Bit 4 : Sa5 Bit of Frame 9 (RSa5F9) Bit 3 : Sa5 Bit of Frame 7 (RSa5F7) Bit 2 : Sa5 Bit of Frame 5 (RSa5F5) Bit 1 : Sa5 Bit of Frame 3 (RSa5F3) Bit 0 : Sa5 Bit of Frame 1 (RSa5F1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RSa6F15 0
RSa6 Received Sa6 Bits 006B, 026B, 046B, 066B
6 RSa6F13 0
5 RSa6F11 0
4 RSa6F9 0
3 RSa6F7 0
2 RSa6F5 0
1 RSa6F3 0
0 RSa6F1 0
Bit 7 : Sa6 Bit of Frame 15 (RSa6F15) Bit 6 : Sa6 Bit of Frame 13 (RSa6F13) Bit 5 : Sa6 Bit of Frame 11 (RSa6F11) Bit 4 : Sa6 Bit of Frame 9 (RSa6F9) Bit 3 : Sa6 Bit of Frame 7 (RSa6F7) Bit 2 : Sa6 Bit of Frame 5 (RSa6F5) Bit 1 : Sa6 Bit of Frame 3 (RSa6F3) Bit 0 : Sa6 Bit of Frame 1 (RSa6F1)
Register Name: Register Description: Address (hex): Bit # Name Default 7 RSa7F15 0
RSa7 Received Sa7 Bits 006C, 026C, 046C, 066C
6 RSa7F13 0
5 RSa7F11 0
4 RSa7F9 0
3 RSa7F7 0
2 RSa7F5 0
1 RSa7F3 0
0 RSa7F1 0
Bit 7 : Sa7 Bit of Frame 15 (RSa4F15) Bit 6 : Sa7 Bit of Frame 13 (RSa7F13) Bit 5 : Sa7 Bit of Frame 11 (RSa7F11) Bit 4 : Sa7 Bit of Frame 9 (RSa7F9) Bit 3 : Sa7 Bit of Frame 7 (RSa7F7) Bit 2 : Sa7 Bit of Frame 5 (RSa7F5) Bit 1 : Sa7 Bit of Frame 3 (RSa7F3) Bit 0 : Sa7 Bit of Frame 1 (RSa7F1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RSa8F15 0
RSa8 Received Sa8 Bits 006D, 026D, 046D, 066D
6 RSa8F13 0
5 RSa8F11 0
4 RSa8F9 0
3 RSa8F7 0
2 RSa8F5 0
1 RSa8F3 0
0 RSa8F1 0
Bit 0 : Sa8 Bit of Frame 1 (RSa8F1) Bit 1 : Sa8 Bit of Frame 3 (RSa8F3) Bit 2 : Sa8 Bit of Frame 5 (RSa8F5) Bit 3 : Sa8 Bit of Frame 7 (RSa8F7) Bit 4 : Sa8 Bit of Frame 9 (RSa8F9) Bit 5 : Sa8 Bit of Frame 11 (RSa8F11) Bit 6 : Sa8 Bit of Frame 13 (RSa8F13) Bit 7 : Sa8 Bit of Frame 15 (RSa8F15)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.13 Receive Framer HDLC Controller
Each transmit and receive framer has an HDLC controller with 64-byte FIFOs. These HDLC controllers are not the same as the controllers in the packet interface block. The HDLC controllers automatically generate and detect flags, generate and check the CRC checksum, generate and detect abort sequences, stuff and destuff zeros, and byte align to the data stream. Register Name: Register Description: Address (hex): Bit # Name Default 7 RCRCD 0
RHC Receive HDLC Control Register 0010, 0210, 0410, 0610
6 RHR 0
5 RHMS 0
4 RHCS4 0
3 RHCS3 0
2 RHCS2 0
1 RHCS1 0
0 RHCS0 0
Bit 0 to Bit 4 : Receive HDLC Channel Select (RHCSx) These bits determine which DS0 is mapped to the HDLC controller when enabled with RHMS = 0. RHCS0 to RHCS4 = all 0s selects channel 1, RHCS0 to RHCS4 = all 1s selects channel 32 (E1). Bit 5 : Receive HDLC Mapping Select (RHMS) 0 = Receive HDLC assigned to channels 1 = Receive HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode) Bit 6 : Receive HDLC Reset (RHR) Will reset the receive HDLC controller and flush the receive FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset receive HDLC controller and flush the receive FIFO Bit 7 : Receive CRC16 Display (RCRCD) 0 = Do not write received CRC16 code to FIFO 1= Write received CRC16 code to FIFO after last octet of packet
Register Name: Register Description: Address (hex): Bit # Name Default 7 BSE8 0
RHBSE Receive HDLC Bit Suppress Register 0011, 0211, 0411, 0611
6 BSE7 0
5 BSE6 0
4 BSE5 0
3 BSE4 0
2 BSE3 0
1 BSE2 0
0 BSE1 0
Bit 0 : Receive Channel Bit 1 Suppress:Sa8 Bit Suppress (BSE1) LSB of the channel. Set to one to stop this bit from being used. Bit 1 : Receive Channel Bit 2 Suppress/Sa7 Bit Suppress (BSE2) Set to one to stop this bit from being used Bit 2 : Receive Channel Bit 3 Suppress/Sa6 Bit Suppress (BSE3) Set to one to stop this bit from being used Bit 3 : Receive Channel Bit 4 Suppress/Sa5 Bit Suppress (BSE4) Set to one to stop this bit from being used Bit 4 : Receive Channel Bit 5 Suppress/Sa4 Bit Suppress (BSE5) Set to one to stop this bit from being used Bit 5 : Receive Channel Bit 6 Suppress (BSE6) Set to one to stop this bit from being used. Bit 6 : Receive Channel Bit 7 Suppress (BSE7) Set to one to stop this bit from being used. Bit 7 : Receive Channel Bit 8 Suppress (BSE8) MSB of the channel. Set to one to stop this bit from being used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.13.1 HDLC FIFO Control Control of the receive FIFO is accomplished via the Receive HDLC FIFO Control Register (RHFC). The FIFO Control register sets the watermarks for the receive FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM is a real-time bit and will remain set as long as the receive FIFO's write pointer is above the watermark. If enabled, this condition can also cause an interrupt via the INT pin. Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RHFC Receive HDLC FIFO Control Register 0087, 0287, 0487, 0687
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 RFHWM1 0
0 RFHWM0 0
Bits 7 to 2: Unused. Must be set = 0 for proper operation. Bits 1 & 0 : Receive FIFO High Watermark Select (RFHWM1 to RFHWM0) RFHWM1 RFHWM0 Receive FIFO Watermark (bytes) 4 16 32 48
0 0 1 1
0 1 0 1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.13.2 Receive Packet Bytes Available The lower 6 bits of the Receive Packet Bytes Available register indicates the number of bytes (0 through 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register the host then checks the HDLC Status register for detailed message status.
If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message then the MSB of the RHPBA register will return a value of 1. This indicates that the host may safely read the number of bytes returned by the lower 6 bits of the RHPBA register but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise). Register Name: Register Description: Address (hex): Bit # Name Default 7 MS 0
RHPBA Receive HDLC Packet Bytes Available Register 00B5, 02B5, 04B5, 06B5
6 RPBA6 0
5 RPBA5 0
4 RPBA4 0
3 RPBA3 0
2 RPBA2 0
1 RPBA1 0
0 RPBA0 0
Bit 7 : Message Status (MS) 0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC Status register for details. 1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the HDLC Status. Bits 6 to 0 : Receive FIFO Packet Bytes Available Count (RPBA6 to RPBA0) RPBA0 is the LSB.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RHD7 0
RHF Receive HDLC FIFO Register 00B6, 02B6, 04B6, 06B6
6 RHD6 0
5 RHD5 0
4 RHD4 0
3 RHD3 0
2 RHD2 0
1 RHD1 0
0 RHD0 0
Bit 7 : Receive HDLC Data Bit 7 (RHD7) MSB of a HDLC packet data byte. Bit 6 : Receive HDLC Data Bit 6 (RHD6) Bit 5 : Receive HDLC Data Bit 5 (RHD5) Bit 4 : Receive HDLC Data Bit 4 (RHD4) Bit 3 : Receive HDLC Data Bit 3 (RHD3) Bit 2 : Receive HDLC Data Bit 2 (RHD2) Bit 1 : Receive HDLC Data Bit 1 (RHD1) Bit 0 : Receive HDLC Data Bit 0 (RHD0) LSB of a HDLC packet data byte.
11.6.13.3 HDLC Status and Information RRTS5 and RLS5 provide status information for the receive HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status register RLS5 has the ability to initiate a hardware interrupt via the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt Mask Register (RIM5). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RRTS5 Receive Real-Time Status 5 (HDLC) 00B4, 02B4, 04B4, 06B4
6 PS2 0
5 PS1 0
4 PS0 0
3 --0
2 -- 0
1 RHWM 0
0 RNE 0
All bits in this register are real-time.
Bit 7 : Unused. Bits 6 to 4 : Receive Packet Status (PS2 to PS0) These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 PS1 PS0 PACKET STATUS In Progress: End of message has not yet been reached. Packet OK: Packet ended with correct CRC codeword. CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword. Abort: Packet ended because an abort signal was detected (7 or more ones in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
Bits 3 & 2 : Unused. Bit 1 : Receive FIFO Above High Watermark Condition (RHWM) Set when the receive 64-byte FIFO fills beyond the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). This is a real-time bit. Bit 0 : Receive FIFO Not Empty Condition (RNE) Set when the receive 64-byte FIFO has at least one byte available for a read. This is a real-time bit.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RLS5 Receive Latched Status Register 5 (HDLC) 0094, 0294, 0494, 0694
6 -- 0
5 ROVR 0
4 RHOBT 0
3 RPE 0
2 RPS 0
1 RHWMS 0
0 RNES 0
Bits 7& 6 : Unused. Bit 5 : Receive FIFO Overrun (ROVR) Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bit 4 : Receive HDLC Opening Byte Event (RHOBT) Set when the next byte available in the receive FIFO is the first byte of a message. Bit 3 : Receive Packet End Event (RPE) Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when read. Bit 2 : Receive Packet Start Event (RPS) Set when the HDLC controller detects an opening byte. This is a latched bit and will be cleared when read. Bit 1 : Receive FIFO Above High Watermark Set Event (RHWMS) Set when the receive 64-byte FIFO crosses the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). Rising edge detect of RHWM. Bit 0 : Receive FIFO Not Empty Set Event (RNES) Set when the receive FIFO has transitioned from `empty' to `not-empty' (at least one byte has been put into the FIFO). Rising edge detect of RNE.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
RIM5 Receive Interrupt Mask 5 (HDLC) 00A4, 02A4, 04A4, 06A4
6 -- 0
5 ROVR 0
4 RHOBT 0
3 RPE 0
2 RPS 0
1 RHWMS 0
0 RNES 0
Bits 7& 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Receive FIFO Overrun (ROVR) 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive HDLC Opening Byte Event (RHOBT) 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive Packet End Event (RPE) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive Packet Start Event (RPS) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive FIFO Above High Watermark Set Event (RHWMS) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive FIFO Not Empty Set Event (RNES) 0 = interrupt masked 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.6.14 Interfacing the E1 Rx Framer to the BERT
Register Name: Register Description: Address (hex): Bit # Name Default 7
--
RBICR Receive BERT Interface Control Register 008A, 028A, 048A, 068A
6
--
5
--
4
--
3
--
0
0
0
0
0
2 RBDC 0
1
--
0
0 RBEN 0
Bits 7 to 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Receive BERT Direction Control (RBDC) 0 = Receive Path: The BERT receives data from the network side via RPOS and RNEG. 1 = Backplane: The BERT receives data from the system backplane via the TSER pin. Bit 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Receive BERT Enable (RBEN) 0 = Receive BERT is disabled. 1 = Receive BERT is enabled.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
RBCS1, RBCS2, RBCS3, RBCS4 Receive BERT Channel Select Registers 00D4 to 00D7, 02D4 to 02D7, 04D4 to 04D7, 06D4 to 06D7
Setting any of the CH1 through CH32 bits in the RBCS1 through RBCS4 registers will map data from those channels to the on-board BERT. RBEN must be set to one for these registers to have effect. Multiple, or all channels may be selected simultaneously. These registers work with the receive-side framer only.
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
(LSB) CH1 CH9 CH17 CH25
RBCS1 RBCS2 RBCS3 RBCS4
Register Name: Register Description: Address (hex): Bit # Name Default 7 BSE8 0
RBBS Receive BERT Bit Suppress Register 008B, 028B, 048B, 068B
6 BSE7 0
5 BSE6 0
4 BSE5 0
3 BSE4 0
2 BSE3 0
1 BSE2 0
0 BSE1 0
Bit 7 : Receive Channel Bit 8 Suppress (BSE8) MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Receive Channel Bit 7 Suppress (BSE7) Set to one to stop this bit from being used. Bit 5 : Receive Channel Bit 6 Suppress (BSE6) Set to one to stop this bit from being used. Bit 4 : Receive Channel Bit 5 Suppress (BSE5) Set to one to stop this bit from being used. Bit 3 : Receive Channel Bit 4 Suppress (BSE4) Set to one to stop this bit from being used. Bit 2 : Receive Channel Bit 3 Suppress (BSE3) Set to one to stop this bit from being used. Bit 1 : Receive Channel Bit 2 Suppress (BSE2) Set to one to stop this bit from being used. Bit 0 : Receive Channel Bit 1 Suppress (BSE1) LSB of the channel. Set to one to stop this bit from being used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7 E1 Transmit framer Table 11-18 E1 Transmit Framer Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0100-010F 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 011A 011B 011C - 011F 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 0130 0131 0132 0133 0134 0135 0136 0137 0138 0139 013A 013B 013C 013D 013E 013F 0140
NAME
FUNCTION
-- THC1 THBSE -- THC2 TSACR -- -- -- SSIE1 SSIE2 SSIE3 SSIE4 TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 TS1
Unused. Must be set = 0 for proper operation. Tx HDLC Control 1 Tx HDLC Bit Suppress Unused. Must be set = 0 for proper operation. Tx HDLC Control 2 Tx Sa Bit Control Register Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Tx Software Signaling Insertion Enable 1 Tx Software Signaling Insertion Enable 2 Tx Software Signaling Insertion Enable 3 Tx Software Signaling Insertion Enable 4 Unused. Must be set = 0 for proper operation. Tx Idle Definition 1 Tx Idle Definition 2 Tx Idle Definition 3 Tx Idle Definition 4 Tx Idle Definition 5 Tx Idle Definition 6 Tx Idle Definition 7 Tx Idle Definition 8 Tx Idle Definition 9 Tx Idle Definition 10 Tx Idle Definition 11 Tx Idle Definition 12 Tx Idle Definition 13 Tx Idle Definition 14 Tx Idle Definition 15 Tx Idle Definition 16 Tx Idle Definition 17 Tx Idle Definition 18 Tx Idle Definition 19 Tx Idle Definition 20 Tx Idle Definition 21 Tx Idle Definition 22 Tx Idle Definition 23 Tx Idle Definition 24 Tx Idle Definition 25 Tx Idle Definition 26 Tx Idle Definition 27 Tx Idle Definition 28 Tx Idle Definition 29 Tx Idle Definition 30 Tx Idle Definition 31 Tx Idle Definition 32 Tx Signaling 1
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0141 0142 0143 0144 0145 0146 0147 0148 0149 014A 014B 014C 014D 014E 014F 0150 0151 0152 0153 0154-0163 0164 0165 0166 0167 0168 0169 016A 016B 016C 016D 016E-017F 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 0190 0191 0192 0193-019E 019F
NAME
FUNCTION
TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3 TCICE4 -- TAF TNAF TSiAF TSiNAF TRA TSa4 TSa5 TSa6 TSa7 TSa8 -- TMMR TCR1 TCR2 TCR3 TIOCR TGCCR -- THFC TDS0SEL TBICR TBBS -- -- TSYNCC TLS1 TLS2 TLS3 -- TIIR
Tx Signaling 2 Tx Signaling 3 Tx Signaling 4 Tx Signaling 5 Tx Signaling 6 Tx Signaling 7 Tx Signaling 8 Tx Signaling 9 Tx Signaling 10 Tx Signaling 11 Tx Signaling 12 Tx Signaling 13 Tx Signaling 14 Tx Signaling 15 Tx Signaling 16 Tx Channel Idle Code Enable 1 Tx Channel Idle Code Enable 2 Tx Channel Idle Code Enable 3 Tx Channel Idle Code Enable 4 Unused. Must be set = 0 for proper operation. Tx Align Frame Tx Non-Align Frame Tx Si bits for Align Frame Tx Si bits for Non-Align Frame Tx Remote Alarm Tx Sa4 Bits Tx Sa5 Bits Tx Sa6 Bits Tx Sa7 Bits Tx Sa8 Bits Unused. Must be set = 0 for proper operation. Tx Master Mode Tx Control 1 Tx Control 2 Tx Control 3 Tx I/O Configuration Tx Gapped Clock Control Unused. Must be set = 0 for proper operation. Tx HDLC FIFO Control Unused. Must be set = 0 for proper operation. Tx DS0 Monitor Select Tx BERT Interface Control Tx BERT Bit Suppress En Unused. Must be set = 0 for proper operation. Unused. Must be set = 0 for proper operation. Tx Synchronizer Control Unused. Must be set = 0 for proper operation. Tx Latched Status 1 Tx Latched Status 2 (HDLC) Tx Latched Status 3 (SYNC) Unused. Must be set = 0 for proper operation. Tx Interrupt Information Register 294 of 362
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 01A0 01A1 01A2 01A3-01B0 01B1 01B2 01B3 01B4 01B5-01BA 01BB 01BC-01C3 01C4 01C5 01C6 01C7 01C8 01C9 01CA 01CB 01CC 01CD 01CE 01CF 01D0 01D1 01D2 01D3 01D4 01D5 01D6 01D7 01D8 - 01FF
NAME
FUNCTION
TIM1 TIM2 TIM3 -- TRTS2 -- TFBA THF -- TDS0M -- TCMR1 TCMR2 TCMR3 TCMR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBCS1 TBCS2 TBCS3 TBCS4 --
Tx Interrupt Mask Register 1 Tx Interrupt Mask Register 2 (HDLC) Tx Interrupt Mask Register 3 (SYNC) Unused. Must be set = 0 for proper operation. Tx Real-Time Status Register 2 (HDLC) Unused. Must be set = 0 for proper operation. Tx HDLC FIFO Buffer Available Tx HDLC FIFO Unused. Must be set = 0 for proper operation. Tx DS0 Monitor Unused. Must be set = 0 for proper operation. Tx Channel Mark 1 Tx Channel Mark 2 Tx Channel Mark 3 Tx Channel Mark 4 Tx Hardware Signaling Channel Select 1 Tx Hardware Signaling Channel Select 2 Tx Hardware Signaling Channel Select 3 Tx Hardware Signaling Channel Select 4 Tx Gapped Clock Channel Select 1 Tx Gapped Clock Channel Select 2 Tx Gapped Clock Channel Select 3 Tx Gapped Clock Channel Select 4 Per-Channel Loopback Enable 1 Per-Channel Loopback Enable 2 Per-Channel Loopback Enable 3 Per-Channel Loopback Enable 4 Tx BERT Channel Select 1 Tx BERT Channel Select 2 Tx BERT Channel Select 3 Tx BERT Channel Select 4 Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.1 Transmit Master Mode Register
The Transmit Master Mode Register (TMMR) controls the initialization of the transmit side formatter. The FRM_EN bit may be left `low' if the formatter for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Address (hex): Bit # Name Default 7
FRM_EN
TMMR Transmit Master Mode Register 0180, 0380, 0580, 0780
6
INIT_DONE
5
--
4
--
3
--
2
--
1
SFTRST
0
T1/E1
0
0
0
0
0
0
0
0
Bit 7 : Framer Enable (FRM_EN) This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled - held in low power state 1 = Framer enabled - all features active Bit 6 : Initialization Done (INIT_DONE) The host (user) must set this bit once he/she has written the configuration registers. The host is required to write or clear all RAM based registers (addresses 100H to 17FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bits 5 to 2 : Unused. Must be set = 0 for proper operation. Bit 1 : Soft Reset (SFTRST) Level sensitive processor reset. Should be taken high then low to reset and initialize the internal processor. 0 = Normal Operation 1 = Hold the internal RISC in reset. This bit only affects the transmit side processor. Bit 0 : Transmitter T1/E1 Mode Select (T1/E1) Sets operating mode for transmitter only! This bit must be written with the desired value prior to setting INIT_DONE. 0 = T1 operation 1 = E1 operation
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.2 Interrupt Information Registers
The Interrupt Information Registers provide an indication of which DS26556 Status Registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt has been serviced and cleared. Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TIIR Transmit Interrupt Information Register 019F, 039F, 059F, 079F
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 TLS3 0
1 TLS2 0
0 TLS1 0
11.7.3 E1 Transmit Control Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 TFPT 0
TCR1 Transmit Control Register 1 0181, 0381, 0581, 0781
6 T16S 0
5 TG802 0
4 TSiS 0
3 TSA1 0
2 THDB3 0
1 TAIS 0
0 TCRC4 0
Bit 7 : Transmit Time Slot 0 Pass Through (TFPT) 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Bit 6 : Transmit Time Slot 16 Data Select (T16S) 0 = time slot 16 determined by the SSIEx and THSCS registers 1 = source time slot 16 from TS1 to TS16 registers Bit 5 : Transmit G.802 Enable (TG802) 0 = do not force TCHMRK high during bit 1 of time slot 26 1 = force TCHMRK high during bit 1 of time slot 26 Bit 4 : Transmit International Bit Select (TSiS) 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.7 must be set to 0) Bit 3 : Transmit Signaling All Ones (TSA1) 0 = normal operation 1 = force time slot 16 in every frame to all ones Bit 2 : Transmit HDB3 Enable (THDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 1 : Transmit AIS (TAIS) 0 = transmit data normally 1 = transmit an unframed all-ones code Bit 0 : Transmit CRC4 Enable (TCRC4) 0 = CRC4 disabled 1 = CRC4 enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 AEBE 0
TCR2 Transmit Control Register 2 0182, 0382, 0582, 0782
6 AAIS 0
5 ARA 0
4 -- 0
3 -- 0
2 -- 0
1 -- 0
0 -- 0
Bit 7 : Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Bit 6 : Automatic AIS Generation (AAIS) 0 = disabled 1 = enabled Bit 5 : Automatic Remote Alarm Generation (ARA) 0 = disabled 1 = enabled Bits 4 to 0 : Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TCR3 Transmit Control Register 3 0183, 0383, 0583, 0783
6 0
5 TCSS1 0
4 TCSS0 0
3 0
2 0
1 IBPV 0
0 CRC4R 0
Bits 7 & 6 : Unused, must be set = 0 for proper operation Bit 5 & 4 : Transmit Clock Source Select bit 1 and 0 (TCSS1, TCSS0)
TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLK pin is always the source of Transmit Clock. Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after 1 channel time. For Future Use Use the signal present at RCLK as the Transmit Clock. The TCLK pin is ignored.
Bits 3 & 2 : Unused, must be set = 0 for proper operation Bit 1 : Insert BPV (IBPV) A 0-to-1 transition on this bit will cause a single BiPolar Violation (BPV) to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 0 : CRC-4 Recalculate (CRC4R) 0 = transmit CRC-4 generation and insertion operates in normal mode 1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TCLKINV 0
TIOCR Transmit I/O Configuration Register 0184, 0384, 0584, 0784
6 TSYNCINV 0
5 HSSYNCINV 0
4 HSCLKM 0
3 HSSM 0
2 TSIO 0
1 -- 0
0 TSM 0
Bit 7 : TCLK Invert (TCLKINV) 0 = No inversion 1 = Invert Bit 6 : TSYNC Invert (TSYNCINV) 0= No inversion 1 = Invert Bit 5 : HSSYNC Invert (HSSYNCINV) 0 = No inversion 1 = Invert Bit 4 : HSYSCLK Mode Select (HSCLKM) 0 = if HSYSCLK is 1.544MHz 1 = if HSYSCLK is 2.048/4.096/8.192/16.384MHz Note: This bit must be set the same as the RIOCR.HSCLKM bit Bit 3 : HSSYNC Mode Select (HSSM) Selects frame or multiframe mode for the HSSYNC pin. 0 = frame mode 1 = multiframe mode Bit 2 : TSYNC I/O Select (TSIO) 0 = TSYNC is an input 1 = TSYNC is an output Bit 1 : Unused, must be set = 0 for proper operation. Bit 0 : TSYNC Mode Select (TSM) Selects frame or multiframe mode for the TSYNC pin when TSYNC is an output. 0 = frame mode 1 = multiframe mode
11.7.4 E1 Transmit Status and Information
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INT signal.
Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits will remain stable, and valid during the host read operation. The current value of the internal status signals can be read at any time from the real-time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a change-of-state for an alarm, condition, or event; and operate in a read-then-write fashion. The user should read the value of the desired status bit, and then write a 1 to that particular bit location in order to clear the latched value (write a `0' to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (TIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs. The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin will clear even if the alarm is still present.
Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TLS1 Transmit Latched Status Register 1 0190, 0390, 0590, 0790
6 0
5 0
4 -- 0
3 TAF 0
2 TMF 0
1 LOTCC 0
0 LOTC 0
All bits in this register are latched and can cause interrupts.
Bits 7 to 4 : Unused Bit 3 : Transmit Align Frame Event (TAF) Set every 250ms at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Bit 2 : Transmit Multiframe Event (TMF) Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. Bit 1 : Loss of Transmit Clock Condition Clear (LOTCC) Set when the LOTC condition has cleared (a clock has been sensed at the TCLK pin). Bit 0 : Loss of Transmit Clock Condition (LOTC) Set when the TCLK pin has not transitioned for approximately 3 clock periods. Will force the LOTC pin high if enabled. The host can clear this bit even if the condition is still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit. If enabled by TIM1.0, the INT pin transitions low when this bit is set, and transitions high when this bit is cleared (if no other unmasked interrupt conditions exist).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 0
TIM1 Transmit Interrupt Mask Register 1 01A0, 03A0, 05A0, 07A0
6 0
5 0
4 0
3 TAF 0
2 TMF 0
1 LOTCC 0
0 LOTC 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Transmit Align Frame Event (TAF) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Transmit Multiframe Event (TMF) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Loss of Transmit Clock Clear Condition (LOTCC) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Loss of Transmit Clock Condition (LOTC) 0 = interrupt masked 1 = interrupt enabled
11.7.5 Per-Channel Loopback
The Per-Channel Loopback Registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. Each of the bit position in the Per-Channel Loopback Registers (PCLR1/PCLR2/PCLR3/PCLR4) represent a time slot in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSER for that channel. Register Name: Register Description: Address (hex): Bit # Name Name Name Name Default 7 CH8 CH16 CH24 CH32 0
PCL1, PCL2, PCL3, PCL4 Per-Channel Loopback Enable Registers 01D0 to 01D3, 03D0 to 03D3, 05D0 to 05D3, 07D0h to 07D3
6 CH7 CH15 CH23 CH31 0
5 CH6 CH14 CH22 CH30 0
4 CH5 CH13 CH21 CH29 0
3 CH4 CH12 CH20 CH28 0
2 CH3 CH11 CH19 CH27 0
1 CH2 CH10 CH18 CH26 0
0 CH1 CH9 CH17 CH25 0
PCL1 PCL2 PCL3 PCL4
Bits 7 to 0 / Per-Channel Loopback Enable for Channels 32 to 1 (CH32 to CH1) 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.6 E1 Transmit DS0 Monitoring Function
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TDS0SEL Transmit DS0 Channel Monitor Select 0189, 0389, 0589, 0789
6 -- 0
5 -- 0
4 TCM4 0
3 TCM3 0
2 TCM2 0
1 TCM1 0
0 TCM0 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bits 4 to 0 : Transmit Channel Monitor Bits (TCM4 to TCM0) TCM0 is the LSB of a 5 bit channel select that determines which transmit channel data will appear in the TDS0M register.
Register Name: Register Description: Address (hex): Bit # Name Default 7 B1 0
TDS0M Transmit DS0 Monitor Register 01BB, 03BB, 05BB, 07BB
6 B2 0
5 B3 0
4 B4 0
3 B5 0
2 B6 0
1 B7 0
0 B8 0
Bits 7 to 0 : Transmit DS0 Channel Bits (B1 to B8) Transmit channel data that has been selected by the Transmit Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.7 E1 Transmit Signaling Operation
Register Name: Register Description: Address (hex):
TS1 TO TS16 Transmit Signaling Registers (E1 MODE) 0140 to 014F, 0340 to 034F, 0540 to 054F, 0740 to 074F
Table 11-19 E1 Transmit Signaling - CAS Format
Bit # Name Name Name Name Name Name Name Name Name Name Name Name Name Name Name Name Default 7 0 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH13-A CH14-A CH15-A 0 6 0 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH13-B CH14-B CH15-B 0 5 0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C 0 4 0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D 0 3 X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A 0 2 Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B 0 1 X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C 0 0 X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D 0
TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
Table 11-20 E1 Transmit Signaling - CCS Format
Bit # Name Name Name Name Name Name Name Name Name Name Name Name Name Name Name Name Default 7 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 0 6 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 0 5 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 0 4 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 0 3 5 13 21 29 37 45 53 61 69 77 85 93 101 109 117 125 0 2 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 0 1 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 0 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 0
TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
SSIE1 Software Signaling Insertion Enable Register 1 0118, 0318, 0518, 0718
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 8 to 8 (CH8 to CH1) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
SSIE2 Software Signaling Insertion Enable Register 2 0119, 0319, 0519, 0719
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 16 to 9 (CH16 TO CH9) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
SSIE3 Software Signaling Insertion Enable Register 3 011A, 031A, 051A, 071A
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 24 to 17 (CH24 TO CH17) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH32 0
SSIE4 Software Signaling Insertion Enable Register 4 011B, 031B, 051B, 071B
6 CH31 0
5 CH30 0
4 CH29 0
3 CH28 0
2 CH27 0
1 CH26 0
0 CH25 0
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 32 to 25 (CH32 TO CH25) These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
Register Name: Register Description: Address (hex): Bit # Name Default 7 CH8 0
THSCS1 Transmit Hardware Signaling Channel Select Register 1 01C8, 03C8, 05C8, 07C8,
6 CH7 0
5 CH6 0
4 CH5 0
3 CH4 0
2 CH3 0
1 CH2 0
0 CH1 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 8 to 1 (CH8 to CH1). This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel Register Name: Register Description: Address (hex): Bit # Name Default 7 CH16 0
THSCS2 Transmit Hardware Signaling Channel Select Register 2 01C9, 03C9, 05C9, 07C9
6 CH15 0
5 CH14 0
4 CH13 0
3 CH12 0
2 CH11 0
1 CH10 0
0 CH9 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 16 to 9 (CH16 to CH9). This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH24 0
THSCS3 Transmit Hardware Signaling Channel Select Register 3 01CA, 03CA, 05CA, 07CA
6 CH23 0
5 CH22 0
4 CH21 0
3 CH20 0
2 CH19 0
1 CH18 0
0 CH17 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 24 to 17 (CH24 to CH17 This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 CH32 0
THSCS4 Transmit Hardware Signaling Channel Select Register 4 01CB, 03CB, 05CB, 07CB
6 CH31 0
5 CH30 0
4 CH29 0
3 CH28 0
2 CH27 0
1 CH26 0
0 CH25 0
Bits 7 to 0 / Transmit Hardware Signaling Channel Select for Channels 32 to 25 (CH32 to CH25). This function is used only on ports configured for high-speed multiplexed TDM bus operation. These bits determine which channels will have signaling data inserted from the HTSIG pin into the demultiplexed data stream from the HTDATA pin.
0 = do not source signaling data from the HTSIG pin for this channel 1 = source signaling data from the HTSIG pin for this channel
11.7.8 E1 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Thirty-two Transmit Idle Definition Registers (TIDR1-TIDR32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-4) are used to enable idle code replacement on a per channel basis. Register Name: Register Description: Address (hex): Bit # Name Default 7 C7 0
TIDR1 to TIDR32 Transmit Idle Code Definition Registers 1 to 32 0120 to 013F, 0320 to 013F, 0520 to 053F, 0720 to 073F
6 C6 0
5 C5 0
4 C4 0
3 C3 0
2 C2 0
1 C1 0
0 C0 0
Bits 7 to 0 : Per-Channel Idle Code Bits (C7 to C0) C0 is the LSB of the Code (this bit is transmitted last).
Register Name: Register Description: Address (hex):
TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers 0150 to 0153, 0350 to 0353, 0550 to 0553, 0750 to 0753
The Transmit Channel Idle Code Enable Registers (TCICE1/2/3/4) are used to determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Idle Code Definition Register. Bit # Name Name Name Name Default 7 CH8 CH16 CH24 CH32 0 6 CH7 CH15 CH23 CH31 0 5 CH6 CH14 CH22 CH30 0 4 CH5 CH13 CH21 CH29 0 3 CH4 CH12 CH20 CH28 0 2 CH3 CH11 CH19 CH27 0 1 CH2 CH10 CH18 CH26 0 0 CH1 CH9 CH17 CH25 0
TCICE1 TCICE2 TCICE3 TCICE4
Bits 7 to 0 : Transmit Channels 32 to 1 Code Insertion Control Bits (CH32 to CH1) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.9 E1 Transmit Channel Mark Registers
The Receive Channel Mark Registers (RCMR1/RCMR2/RCMR3/RCMR4) and the Transmit Channel Mark Registers (TCMR1/TCMR2/TCMR3/TCMR4) control the mapping of channels to the cell/packet interface and the RCHMRK and TCHMRK pins. The RCHMRK and TCHMRK signals are internally used to select which channels will be mapped to the cell/packet interface. Externally, the signal can be used to multiplex TDM data into channels not used by the cell/packet interface. When the appropriate bits are set to 1, the cell/packet function is mapped to that channel and externally the RCHMRK and TCHMRK pin is held high during the entire corresponding channel time. When used in T1 mode, only RCMR1 to RCMR3 and the LSB of RCMR4 are used. Register Name: Register Description: Address (hex): Bit # Name Name Name Name Default 7 CH8 CH16 CH24 CH32 0
TCMR1, TCMR2, TCMR3, TCMR4 Transmit Channel Mark Registers 01C4 to 01C7, 03C4 to 03C7, 05C4 to 05C7, 07C4 to 07C7
6 CH7 CH15 CH23 CH31 0
5 CH6 CH14 CH22 CH30 0
4 CH5 CH13 CH21 CH29 0
3 CH4 CH12 CH20 CH28 0
2 CH3 CH11 CH19 CH27 0
1 CH2 CH10 CH18 CH26 0
0 CH1 CH9 CH17 CH25 0
TCMR1 TCMR2 TCMR3 TCMR4
Bits 7 to 0 : Transmit Channels 32 to 1 Channel Mark Control Bits (CH32 to CH1) 0 = force the TCHMRK pin to remain low during this channel time 1 = force the TCHMRK pin high during this channel time
Register Name: Register Description: Address (hex): Bit # Name Default 7 TDATFMT 0
TGCCR Transmit Gapped Clock Control Register 0185, 0385, 0585, 0785
6 TGCLKEN 0
5 0
4 0
3 0
2 0
1 0
0 0
Bit 7 : Transmit Channel Data Format (TDATFMT) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) Bit 6 : Transmit Gapped Clock Enable (TGPCKEN) ) If the TCHMRK pin is in the channel clock mode then this bit determines if TCHMRK outputs a pulse during the LSB of all channels or a gapped clock during selected channels. 0 = pulse during LSB of all 1 = gapped clock during selected channels Bits 5 to 0 : Unused. Must be set = 0 for proper operation.
11.7.10 Fractional E1 Support (Gapped Clock Mode)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Name Name Name Default 7 CH8 CH16 CH24 CH32 0
TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 01CC to 01CF, 03CC to 03CF, 05CC to 05CF, 07CC to 07CF
6 CH7 CH15 CH23 CH31 0
5 CH6 CH14 CH22 CH30 0
4 CH5 CH13 CH21 CH29 0
3 CH4 CH12 CH20 CH28 0
2 CH3 CH11 CH19 CH27 0
1 CH2 CH10 CH18 CH26 0
0 CH1 CH9 CH17 CH25 0
TGCCS1 TGCCS2 TGCCS3 TGCCS4
Bits 7 to 0 : Transmit Channels 32 to 1 Gapped Clock Channel Select Bits (CH32 to CH1) 0 = no clock is present on TCHMRK during this channel time 1 = output a clock on TCHMRK during this channel time. The clock will be synchronous with TCLK.
11.7.11 Additional (Sa) and International (Si) Bit Operation (E1 Mode)
Register Name: Register Description: Address (hex): Bit # Name Default 7 Si 0
TAF Transmit Align Frame Register 0164, 0364, 0564, 0764
6 0 0
5 0 0
4 1 1
3 1 1
2 0 0
1 1 1
0 1 1
Bit 7 : International Bit (Si) Bit 6 : Frame Alignment Signal Bit (0) Bit 5 : Frame Alignment Signal Bit (0) Bit 4 : Frame Alignment Signal Bit (1) Bit 3 : Frame Alignment Signal Bit (1) Bit 2 : Frame Alignment Signal Bit (0) Bit 1 : Frame Alignment Signal Bit (1) Bit 0 : Frame Alignment Signal Bit (1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 Si 0
TNAF Transmit Non-Align Frame Register 0165, 0365, 0565, 0765
6 1 1
5 A 0
4 Sa4 0
3 Sa5 0
2 Sa6 0
1 Sa7 0
0 Sa8 0
Bit 7 : International Bit (Si) Bit 6 : Frame Non-Alignment Signal Bit (1) Bit 5 : Remote Alarm [used to transmit the alarm (A)] Bit 4 : Additional Bit 4 (Sa4) Bit 3 : Additional Bit 5 (Sa5) Bit 2 : Additional Bit 6 (Sa6) Bit 1 : Additional Bit 7 (Sa7) Bit 0 : Additional Bit 8 (Sa8)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TSiF14 0
TSiAF Transmit Si Bits of the Align Frame 0166, 0366, 0566 ,0766
6 TSiF12 0
5 TSiF10 0
4 TSiF8 0
3 TSiF6 0
2 TSiF4 0
1 TSiF2 0
0 TSiF0 0
Bit 7 : Si Bit of Frame 14 (TSiF14) Bit 6 : Si Bit of Frame 12 (TSiF12) Bit 5 : Si Bit of Frame 10 (TSiF10) Bit 4 : Si Bit of Frame 8 (TSiF8) Bit 3 : Si Bit of Frame 6 (TSiF6) Bit 2 : Si Bit of Frame 4 (TSiF4) Bit 1 : Si Bit of Frame 2 (TSiF2) Bit 0 : Si Bit of Frame 0 (TSiF0)
Register Name: Register Description: Address (hex): Bit # Name Default 7 TSiF15 0
TSiNAF Transmit Si Bits of the Non-Align Frame 0167, 0367, 0567, 0767
6 TSiF13 0
5 TSiF11 0
4 TSiF9 0
3 TSiF7 0
2 TSiF5 0
1 TSiF3 0
0 TSiF1 0
Bit 7 : Si Bit of Frame 15 (TSiF15) Bit 6 : Si Bit of Frame 13 (TSiF13) Bit 5 : Si Bit of Frame 11 (TSiF11) Bit 4 : Si Bit of Frame 9 (TSiF9) Bit 3 : Si Bit of Frame 7 (TSiF7) Bit 2 : Si Bit of Frame 5 (TSiF5) Bit 1 : Si Bit of Frame 3 (TSiF3) Bit 0 : Si Bit of Frame 1 (TSiF1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TRAF15 0
TRA Transmit Remote Alarm 0168, 0368, 0568, 0768
6 TRAF13 0
5 TRAF11 0
4 TRAF9 0
3 TRAF7 0
2 TRAF5 0
1 TRAF3 0
0 TRAF1 0
Bit 7 : Remote Alarm Bit of Frame 15 (TRAF15) Bit 6 : Remote Alarm Bit of Frame 13 (TRAF13) Bit 5 : Remote Alarm Bit of Frame 11 (TRAF11) Bit 4 : Remote Alarm Bit of Frame 9 (TRAF9) Bit 3 : Remote Alarm Bit of Frame 7 (TRAF7) Bit 2 : Remote Alarm Bit of Frame 5 (TRAF5) Bit 1 : Remote Alarm Bit of Frame 3 (TRAF3) Bit 0 : Remote Alarm Bit of Frame 1 (TRAF1)
Register Name: Register Description: Address (hex): Bit # Name Default 7
TSa4F15
TSa4 Transmit Sa4 Bits 0169, 0369, 0569 ,0769
6
TSa4F13
5
TSa4F11
4
TSa4F9
3
TSa4F7
2
TSa4F5
1
TSa4F3
0
TSa4F1
0
0
0
0
0
0
0
0
Bit 7 : Sa4 Bit of Frame 15 (TSa4F15) Bit 6 : Sa4 Bit of Frame 13 (TSa4F13) Bit 5 : Sa4 Bit of Frame 11 (TSa4F11) Bit 4 : Sa4 Bit of Frame 9 (TSa4F9) Bit 3 : Sa4 Bit of Frame 7 (TSa4F7) Bit 2 : Sa4 Bit of Frame 5 (TSa4F5) Bit 1 : Sa4 Bit of Frame 3 (TSa4F3) Bit 0 : Sa4 Bit of Frame 1 (TSa4F1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TSa5F15 0
TSa5 Transmitted Sa5 Bits 016A, 036A, 056A ,076A
6 TSa5F13 0
5 TSa5F11 0
4 TSa5F9 0
3 TSa5F7 0
2 TSa5F5 0
1 TSa5F3 0
0 TSa5F1 0
Bit 7 : Sa5 Bit of Frame 15 (TSa5F15) Bit 6 : Sa5 Bit of Frame 13 (TSa5F13) Bit 5 : Sa5 Bit of Frame 11 (TSa5F11) Bit 4 : Sa5 Bit of Frame 9 (TSa5F9) Bit 3 : Sa5 Bit of Frame 7 (TSa5F7) Bit 2 : Sa5 Bit of Frame 5 (TSa5F5) Bit 1 : Sa5 Bit of Frame 3 (TSa5F3) Bit 0 : Sa5 Bit of Frame 1 (TSa5F1)
Register Name: Register Description: Address (hex): Bit # Name Default 7 TSa6F15 0
TSa6 Transmit Sa6 Bits 016B, 036B, 056B, 076B
6 TSa6F13 0
5 TSa6F11 0
4 TSa6F9 0
3 TSa6F7 0
2 TSa6F5 0
1 TSa6F3 0
0 TSa6F1 0
Bit 7 : Sa6 Bit of Frame 15 (TSa6F15) Bit 6 : Sa6 Bit of Frame 13 (TSa6F13) Bit 5 : Sa6 Bit of Frame 11 (TSa6F11) Bit 4 : Sa6 Bit of Frame 9 (TSa6F9) Bit 3 : Sa6 Bit of Frame 7 (TSa6F7) Bit 2 : Sa6 Bit of Frame 5 (TSa6F5) Bit 1 : Sa6 Bit of Frame 3 (TSa6F3) Bit 0 : Sa6 Bit of Frame 1 (TSa6F1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TSa7F15 0
TSa7 Transmit Sa7 Bits 016C, 036C, 056C, 076C
6 TSa7F13 0
5 TSa7F11 0
4 TSa7F9 0
3 TSa7F7 0
2 TSa7F5 0
1 TSa7F3 0
0 TSa7F1 0
Bit 7 : Sa7 Bit of Frame 15 (TSa4F15) Bit 6 : Sa7 Bit of Frame 13 (TSa7F13) Bit 5 : Sa7 Bit of Frame 11 (TSa7F11) Bit 4 : Sa7 Bit of Frame 9 (TSa7F9) Bit 3 : Sa7 Bit of Frame 7 (TSa7F7) Bit 2 : Sa7 Bit of Frame 5 (TSa7F5) Bit 1 : Sa7 Bit of Frame 3 (TSa7F3) Bit 0 : Sa7 Bit of Frame 1 (TSa7F1)
Register Name: Register Description: Address (hex): Bit # Name Default 7 TSa8F15 0
TSa8 Transmit Sa8 Bits 016D, 036D, 056D ,076D
6 TSa8F13 0
5 TSa8F11 0
4 TSa8F9 0
3 TSa8F7 0
2 TSa8F5 0
1 TSa8F3 0
0 TSa8F1 0
Bit 7 : Sa8 Bit of Frame 15 (TSa8F15) Bit 6 : Sa8 Bit of Frame 13 (TSa8F13) Bit 5 : Sa8 Bit of Frame 11 (TSa8F11) Bit 4 : Sa8 Bit of Frame 9 (TSa8F9) Bit 3 : Sa8 Bit of Frame 7 (TSa8F7) Bit 2 : Sa8 Bit of Frame 5 (TSa8F5) Bit 1 : Sa8 Bit of Frame 3 (TSa8F3) Bit 0 : Sa8 Bit of Frame 1 (TSa8F1)
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 SiAF 0
TSACR Transmit Sa Bit Control Register 0114, 0314, 0514, 0714
6 SiNAF 0
5 RA 0
4 Sa4 0
3 Sa5 0
2 Sa6 0
1 Sa7 0
0 Sa8 0
Bit 7 : International Bit in Align Frame Insertion Control Bit (SiAF) 0 = do not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream Bit 6 : International Bit in Non-Align Frame Insertion Control Bit (SiNAF) 0 = do not insert data from the TSiNAF register into the transmit data stream 1 = insert data from the TSiNAF register into the transmit data stream Bit 5 : Remote Alarm Insertion Control Bit (RA) 0 = do not insert data from the TRA register into the transmit data stream 1 = insert data from the TRA register into the transmit data stream Bit 4 : Additional Bit 4 Insertion Control Bit (Sa4) 0 = do not insert data from the TSa4 register into the transmit data stream 1 = insert data from the TSa4 register into the transmit data stream Bit 3 : Additional Bit 5 Insertion Control Bit (Sa5) 0 = do not insert data from the TSa5 register into the transmit data stream 1 = insert data from the TSa5 register into the transmit data stream Bit 2 : Additional Bit 6 Insertion Control Bit (Sa6) 0 = do not insert data from the TSa6 register into the transmit data stream 1 = insert data from the TSa6 register into the transmit data stream Bit 1 : Additional Bit 7 Insertion Control Bit (Sa7) 0 = do not insert data from the TSa7 register into the transmit data stream 1 = insert data from the TSa7 register into the transmit data stream Bit 0 : Additional Bit 8 Insertion Control Bit (Sa8) 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.12 E1 Transmit HDLC Controller
Register Name: Register Description: Address (hex): Bit # Name Default 7 NOFS 0
THC1 Transmit HDLC Control Register 1 0110, 0310, 0510, 0710
6 TEOML 0
5 THR 0
4 THMS 0
3 TFS 0
2 TEOM 0
1 TZSD 0
0 TCRCD 0
Bit 7 : Number Of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Bit 6 : Transmit End of Message and Loop (TEOML) To loop on a message, should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to the end of all messages. Bit 5 : Transmit HDLC Reset (THR) Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset transmit HDLC controller and flush the transmit FIFO Bit 4 : Transmit HDLC Mapping Select (THMS) 0 = Transmit HDLC assigned to channels 1 = Transmit HDLC assigned to FDL(T1 mode), Sa Bits(E1 mode) Bit 3 : Transmit Flag/Idle Select (TFS) This bit selects the inter-message fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 2 : Transmit End of Message (TEOM) Should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a 2byte CRC code to the end of the message. Bit 1 : Transmit Zero Stuffer Defeat (TZSD) The Zero Stuffer function automatically inserts a zero in the message field (between the flags) after 5 consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (destuffs) any zero after 5 ones in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Bit 0 : Transmit CRC Defeat (TCRCD) A 2-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TABT 0
THC2 Transmit HDLC Control Register 2 0113, 0313, 0513, 0713
6 -- 0
5 THCEN 0
4 THCS4 0
3 THCS3 0
2 THCS2 0
1 THCS1 0
0 THCS0 0
Bit 7 : Transmit Abort (TABT) A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Bit 6 : Unused. Must be set = 0 for proper operation. Bit 5 : Transmit HDLC Controller Enable (THCEN) 0 = Transmit HDLC Controller is not enabled 1 = Transmit HDLC Controller is enabled Bits 4 to 0 : Transmit HDLC Channel Select (THCS4 to 0) Determines which DSO channel will have the carry the HDLC message if enabled.
Register Name: Register Description: Address (hex): Bit # Name Default 7 TBSE8 0
THBSE Transmit HDLC Bit Suppress 0111, 0311, 0511, 0711
6 TBSE7 0
5 TBSE6 0
4 TBSE5 0
3 TBSE4 0
2 TBSE3 0
1 TBSE2 0
0 TBSE1 0
Bit 7 : Transmit Bit 8 Suppress (TBSE8) MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Transmit Bit 7 Suppress (TBSE7) Set to one to stop this bit from being used. Bit 5 : Transmit Bit 6 Suppress (TBSE6) Set to one to stop this bit from being used. Bit 4 : Transmit Bit 5 Suppress/Sa4 Bit Suppress (TBSE5) Set to one to stop this bit from being used Bit 3 : Transmit Bit 4 Suppress/Sa5 Bit Suppress (TBSE4) Set to one to stop this bit from being used Bit 2 : Transmit Bit 3 Suppress/Sa6 Bit Suppress (TBSE3) Set to one to stop this bit from being used Bit 1 : Transmit Bit 2 Suppress/Sa7 Bit Suppress (TBSE2) Set to one to stop this bit from being used Bit 0 : Transmit Bit 1 Suppress/Sa8 Bit Suppress (TBSE1) LSB of the channel. Set to one to stop this bit from being used. 11.7.12.1 Transmit HDLC FIFO Control Control of the transmit FIFO is accomplished via the Transmit HDLC FIFO Control (THFC). The FIFO Control register sets the watermarks for the receive FIFO.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register will be set. TLWM is a real-time bit and will remain set as long as the transmit FIFO's write pointer is below the watermark. If enabled, this condition can also cause an interrupt via the INT pin.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
THFC Transmit HDLC FIFO Control Register 0187, 0387, 0587, 0787
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 TFLWM1 0
0 TFLWM0 0
Bits 7 to 2 : Unused. Must be set = 0 for proper operation. Bits 1 & 0 : Transmit HDLC FIFO Low-Watermark Select (TFLWM1 to TFLWM0) TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Transmit FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes
11.7.12.2 HDLC Status and Information TLS2 provides status information for the transmit HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are latched and some are real-time bits that are not latched. This section contains register descriptions that list which bits are latched and which are real time. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status register, TLS2has the ability to initiate a hardware interrupt via the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt Mask Register (TIM2). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TRTS2 Transmit Real-Time Status Register 2 (HDLC) 01B1, 03B1, 05B1, 07B1
6 -- 0
5 -- 0
4 -- 0
3 TEMPTY 0
2 TFULL 0
1 TLWM 0
0 TNF 0
All bits in this register are real time.
Bits 7 to 4 : Unused. Bit 3 : Transmit FIFO Empty (TEMPTY) A real-time bit that is set high when the FIFO is empty. Bit 2 : Transmit FIFO Full (TFULL) A real-time bit that is set high when the FIFO is full. Bit 1 : Transmit FIFO Below Low-Watermark Condition (TLWM) Set when the transmit 64-byte FIFO empties below the low watermark as defined by the Transmit Low-Watermark bits (TLWM). Bit 0 : Transmit FIFO Not Full Condition (TNF) Set when the transmit 64-byte FIFO has at least one byte available.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TLS2 Transmit Latched Status Register 2 (HDLC) 0191, 0391, 0591, 0791
6 -- 0
5 -- 0
4 -- 0
3 TUDR 0
2 TMEND 0
1 TLWMS 0
0 TNFS 0
All bits in this register are latched and can create interrupts.
Bits 7 to 4 : Unused. Bit 3 : Transmit FIFO Underrun Event (TUDR) Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. Bit 2 : Transmit Message End Event (TMEND) Set when the transmit HDLC controller has finished sending a message. Bit 1 : Transmit FIFO Below Low-Watermark Set Condition (TLWMS) Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low-Watermark bits (TLWM) (rising edge detect of TLWM). Bit 0 : Transmit FIFO Not Full Set Condition (TNFS) Set when the transmit 64-byte FIFO has at least one empty byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TIM2 Transmit Interrupt Mask Register 2 01A1, 03A1, 05A1, 07A1
6 -- 0
5 -- 0
4 -- 0
3 TUDR 0
2 TMEND 0
1 TLWMS 0
0 TNFS 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : Transmit FIFO Underrun Event (TUDR) 0 = interrupt masked 1 = interrupt enabled Bit 2 : Transmit Message End Event (TMEND) 0 = interrupt masked 1 = interrupt enabled Bit 1 : Transmit FIFO Below Low Watermark Set Condition (TLWMS) 0 = interrupt masked 1 = interrupt enabled Bit 0 : Transmit FIFO Not Full Set Condition (TNFS) 0 = interrupt masked 1 = interrupt enabled 11.7.12.3 FIFO Information The Transmit FIFO Buffer Available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TFBA Transmit HDLC FIFO Buffer Available 01B3, 03B3, 05B3, 07B3
6 TFBA6 0
5 TFBA5 0
4 TFBA4 0
3 TFBA3 0
2 TFBA2 0
1 TFBA1 0
0 TFBA0 0
Bit 7 : Unused. Bits 6 to 0 : Transmit FIFO Bytes Available (TFBA6 to TFBA0) TFBA0 is the LSB.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 THD7 0
THF Transmit HDLC FIFO 01B4, 03B4, 05B4, 07B4
6 THD6 0
5 THD5 0
4 THD4 0
3 THD3 0
2 THD2 0
1 THD1 0
0 THD0 0
Bit 7 : Transmit HDLC Data Bit 7 (THD7) MSB of a HDLC packet data byte. Bit 6 : Transmit HDLC Data Bit 6 (THD6) Bit 5 : Transmit HDLC Data Bit 5 (THD5) Bit 4 : Transmit HDLC Data Bit 4 (THD4) Bit 3 : Transmit HDLC Data Bit 3 (THD3) Bit 2 : Transmit HDLC Data Bit 2 (THD2) Bit 1 : Transmit HDLC Data Bit 1 (THD1) Bit 0 : Transmit HDLC Data Bit 0 (THD0) LSB of a HDLC packet data byte.
11.7.13 Interfacing the E1 Transmitter to the BERT
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TBICR Transmit BERT Interface Control Register 018A, 038A, 058A, 078A
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 TBDC 0
1 -- 0
0 TBEN 0
Bits 7 to 3 : Unused. Must be set = 0 for proper operation. Bit 2 : Transmit BERT Direction Control (TBDC) 0 = Transmit Path: The BERT transmits toward the network. 1 = Backplane: The BERT transmits toward the system backplane. Bit 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Transmit BERT Enable (TBEN) 0 = Transmit BERT is disabled. 1 = Transmit BERT is enabled.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex):
TBCS1, TBCS2, TBCS3, TBCS4 Transmit BERT Channel Select Registers 01D4 to 01D7, 03D4 to 03D7, 05D4 to 05D7, 07D4 to 07D7
Setting any of the CH1 through CH32 bits in the TBCS1 through TBCS4 registers will map data into those channels from the on-board BERT. TBEN must be set to one for these registers to have effect. Multiple, or all channels may be selected simultaneously. These registers work with the transmit-side framer only. Bit # Name Name Name Name Default 7 CH8 CH16 CH24 CH32 0 6 CH7 CH15 CH23 CH31 0 5 CH6 CH14 CH22 CH30 0 4 CH5 CH13 CH21 CH29 0 3 CH4 CH12 CH20 CH28 0 2 CH3 CH11 CH19 CH27 0 1 CH2 CH10 CH18 CH26 0 0 CH1 CH9 CH17 CH25 0
TBCS1 TBCS2 TBCS3 TBCS4
Register Name: Register Description: Address (hex): Bit # Name Default 7 BSE8 0
TBBS Transmit BERT Bit Suppress Register 018B, 0038B, 058B, 078B
6 BSE7 0
5 BSE6 0
4 BSE5 0
3 BSE4 0
2 BSE3 0
1 BSE2 0
0 BSE1 0
Bit 7 : Transmit Channel Bit 8 Suppress (BSE8) MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Transmit Channel Bit 7 Suppress (BSE7) Set to one to stop this bit from being used. Bit 5 : Transmit Channel Bit 6 Suppress (BSE6) Set to one to stop this bit from being used. Bit 4 : Transmit Channel Bit 5 Suppress (BSE5) Set to one to stop this bit from being used. Bit 3 : Transmit Channel Bit 4 Suppress (BSE4) Set to one to stop this bit from being used. Bit 2 : Transmit Channel Bit 3 Suppress (BSE3) Set to one to stop this bit from being used. Bit 1 : Transmit Channel Bit 2 Suppress (BSE2) Set to one to stop this bit from being used. Bit 0 : Transmit Channel Bit 1 Suppress (BSE1) LSB of the channel. Set to one to stop this bit from being used.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7.14 E1 Transmit Synchronizer
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TSYNCC Transmit Synchronizer Control Register 018E, 038E, 058E, 078E
6 -- 0
5 -- 0
4 -- 0
3 CRC4 0
2 TSEN 0
1 SYNCE 0
0 RESYNC 0
Bits 7 to 4 : Unused. Must be set = 0 for proper operation. Bit 3 : CRC4 Enable (RCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 2 : Transmit Synchronizer Enable (TSEN) 0 = transmit synchronizer disabled 1 = transmit synchronizer enabled Bit 1 : Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 0 : Resynchronize (RESYNC) When toggled from low to high, a resynchronization of the transmit-side framer is initiated. Must be cleared and set again for a subsequent resync.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TLS3 Transmit Latched Status Register 3 (Synchronizer) 0192, 0392, 0592, 0792
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 LOF 0
0 LOFD 0
Bits 7 to 2 : Unused. Bit 1 : Loss of Frame (LOF) A real-time bit that indicates that the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bit 0 : Loss-of-Frame Synchronization Detect (LOFD) This latched bit is set when the transmit synchronizer is searching for the sync pattern in the incoming data stream.
Register Name: Register Description: Address (hex): Bit # Name Default 7 -- 0
TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) 01A2, 03A2, 05A2, 07A2
6 -- 0
5 -- 0
4 -- 0
3 -- 0
2 -- 0
1 -- 0
0 LOFD 0
Bits 7 to 1 : Unused. Must be set = 0 for proper operation. Bit 0 : Loss-of-Frame Synchronization Detect (LOFD) 0 = Interrupt masked 1 = Interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
12 LINE INTERFACE UNIT (LIU)
Table 12-1 LIU Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 0800 0801 0802 0803 0804 0805 0806 0807 0808-080F
NAME
DESCRIPTION
LCCR1 LTCR LCCR2 LRSR LSIMR LLSR LRSL LRCR -
LIU Common Control Register 1 LIU Transmit Control Register LIU Common Control Register 2 LIU Real Status Register LIU Status Interrupt Mask Register LIU Latched Status Register LIU Receive Signal Level LIU Receive Control Register Unused. Must be set = 0 for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
12.1 LIU Registers
Register Name: Register Description: Address (hex): Bit # Name Default 7 -0
LCCR1 LIU Common Control Register 1 0800, 0A00, 0C00, 0E00
6 -0
5 -0
4 JADS 0
3 JAPS1 0
2 JAPS0 0
1 LMODE 0
0 LSC 0
Bits 7 to 5 : Unused. Must be set = 0 for proper operation. Bit 4 : Jitter Attenuator Depth Select (JADS) 0 = JA FIFO depth set to 128 bits. 1 = JA FIFO depth set to 32 bits. Bits 3 & 2 : Jitter Attenuator Position Select 1 and 0 (JAPS1, JAPS0) Used to select the position of the jitter attenuator. JAPS1 0 0 1 1 JAPS0 0 1 0 1 Function JA in the receive path JA in the transmit path JA is not used JA is not used
Bit 1 : LIU Mode Selection (LMODE) 0 = E1 LIU functions and pulse shapes are selected. 1 = T1/J1 LIU functions and pulse shapes are selected. Bit 0 : LOS Criteria Selection (LCS) This bit is used for LOS Selection Criteria. In E1 Mode, if set this bit uses ETSI (300233) mode selections. If reset, this bit uses G.775 criteria. In T1/J1 Mode, T1.231 criteria are selected.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Address (hex): Bit # Name Default 7 0
LTCR LIU Transmit Control Register 0801, 0A01, 0C01, 0E01
6 ITTIOFF 0
5 TIMPL1 0
4 TIMPL0 0
3 0
2 TPSS2 0
1 TPSS1 0
0 TPSS0 0
Bit 7 : Unused. Must be set = 0 for proper operation. Bit 6 : Internal Transmit Terminating Impedance Off (ITTIOFF) If this bit is set, the transmit load impedance is turned off. Note that the user cable impedance has to be specified by TIMPL bits. The transmitter performance will not be optimum if the transmitter cable impedance (TIMPL2 to 0 bits) is not specified. Bits 5 & 4 : Transmit Load Impedance 1 and 0 (TIMPL1, TIMPL0) Used to select the transmit load source impedance. These have to be set according to the cable impedance. Even if the Internal Load Impedance is turned off (via ITTIOFF), the external cable impedance must be specified for optimum operation by TIMPL1 and TIMPL0. 110W with T1 selection is the J1 Mode.
Table 12-2 Internal Transmit Termination Select
TIMPL1 TIMPLO TRANSMIT TERMINATION (W) 75 100 110 120
0 0 1 1
0 1 0 1
Bit 3 : Unused. Must be set = 0 for proper operation. Bits 2 to 0 : Transmit Pulse Shape Selection 2, 1 and 0 (TPSS2, TPSS1, TPSS0) Used to select the transmit pulse shape. The pulse shape has voltage level and load impedance associated with it once the T1/J1/ E1 selection is made by settings in the LCCR register.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Table 12-3 E1 Transmit Pulse Shape Selection
TPSS2 0 0 TPSS1 0 0 TPSS0 0 1 APPLICATION 75W Coaxial 120W Twisted pair
Table 12-4 T1/J1 Transmit Pulse Shape Selection
TPSS2 0 0 0 0 0 1 1 1 1 TPSS1 0 0 0 1 1 0 0 1 1 TPSS0 0 0 1 0 1 0 1 0 1 APPLICATION Long Haul (0dB) 0-133 ft DSX 133-266 ft DSX 266-399 ft DSX 399-533 ft DSX 533-655 ft DSX 1 -7.5 dB CSU 1 -15 dB CSU 1 -22.5 dB CSU
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 TAIS 0
LCCR2 LIU Common Control Register 2 0802, 0A02, 0C02, 0E02
6 ATAIS 0
5 LLB 0
4 ALB 0
3 RLB 0
2 TPDE 0
1 RPDE 0
0 TE 0
Bit 7 :Transmit AIS (TAIS) If this bit is set AIS is sent using MCLK as the reference clock. The data coming from the framer is replaced by all ones data. Bit 6 : Automatic Transmit AIS (ATAIS) If this bit is set AIS is sent using MCLK as the reference clock if there is a LOS. The data coming from the Framer is replaced by all ones data. Bit 5 : Local Loopback (LLB) Bit 4 : Analog Loopback (ALB) Bit 3 : Remote Loopback (RLB) Bit 2 : Transmit Power-Down Enable (TPDE) Setting this bit will power-down the transmit LIU and tri-state TTIP and TRING. Bit 1 : Receiver Power-Down Enable (RPDE) If this bit is set the receiver LIU for the transceiver is powered down. Bit 0 : Transmit Enable (TE ) If this bit is set the transmitter output for the transceiver is enabled. This function is overridden by the TXEnable pin. If it is low, the TTIP/TRING are always High-Z.
Register Name: Register Description: Address (hex): Bit # Name Default 7 0
LRSR LIU Real Status Register 0803, 0A03, 0C03, 0E03
6 0
5 OEQ 0
4 UEQ 0
3 0
2 SCS 0
1 OCS 0
0 LOSS 0
Bits 7 to 6 : Unused. Bit 5 : (OEQ) Bit 4 : (UEQ) Bit 3 : Unused. Bit 2 : Open Circuit Status (OCS) If this bit is set, it indicates that there is an open circuit at the transmit driver for the transceiver. Please consult the factory for open circuit detection details if the transmitter is configured with impedance match on and CSU filters are selected. Bit 1 : Short Circuit Status (SCS) If this bit is set, it indicates that there is short circuit at the transmit driver for the transceiver. The short circuit resistance has to be 25W (typ) for short circuit detection Bit 0 : Loss of Signal Status (LOS) If this bit is set it indicates LOS for the transceiver.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 JALTRSIM 0
LSIMR LIU Status Interrupt Mask Register 0804, 0A04, 0C04, 0E04
6 OCSRIM 0
5 SCSRIM 0
4 LOSRIM 0
3 JALTSSIM 0
2 OCSSIM 0
1 SCSSIM 0
0 LOSSIM 0
Bit 7 : Jitter Attenuator Limit Trip Reset Status Interrupt Mask (JALTRIM) If this bit is set, Jitter Attenuator Limit Trip Status reset can generate an Interrupt. Bit 6 : Open Circuit Status Reset Interrupt Mask (OCSRIM) If this bit is set, Open circuit Status reset can generate an Interrupt. Bit 5 : Short Circuit Status Reset Interrupt Mask (SCSRIM) If this bit is set, Short circuit Status reset can generate an Interrupt. Bit 4 : Loss of Signal Status Reset Interrupt Mask (LOSRIM) If this bit is set, LOS Status resets can generate an Interrupt. Bit 3 : Jitter Attenuator Limit Trip Set Status Interrupt Mask (JALTSSIM) If this bit is set, Jitter Attenuator Limit Trip Status changes can generate an Interrupt. Bit 2 : Open circuit Status Set Interrupt Mask (OCSSIM) If this bit is set, Open circuit Status changes can generate an Interrupt. Bit 1 : Short Circuit Status Set Interrupt Mask (SCSSIM) If this bit is set, Short circuit Status changes can generate an Interrupt. Bit 0 : Loss of Signal Status Set Interrupt Mask (LOSSIM) If this bit is set, LOS Status changes can generate an Interrupt.
Register Name: Register Description: Address (hex): Bit # Name Default 7 JFLTRLS 0
LLSR LIU Latched Status Register 0805, 0A05, 0C05, 0E05
6 OCRLS 0
5 SCRLS 0
4 LOSRLS 0
3 JALTSLS 0
2 OCSLS 0
1 SCSLS 0
0 LOSSLS 0
Bit 7 : Jitter Attenuator Limit Trip Reset Latched Status (JALTRLS) This bit is set if Jitter Attenuator Trip Status bit reset. Bit 6 : Open Circuit Reset Latched Status (OCRLS) This bit is set if Open Circuit Status bit reset. Bit 5: Short Circuit Reset Latched Status (SCRLS) This bit is set if the Short Circuit Status bit reset. Bit 4 : Loss of Signal Reset Latched Status (LOSRLS) This bit is set if the Short Circuit Status bit reset. Bit 3 : Jitter Attenuator Limit Trip Set Latched Status (JFLTLS) This bit is set if the Jitter Attenuator Trip Status bit is set. Bit 2 : Open Circuit Set Latched Status (OCSLS) This bit is set when Open circuit status bit is set. Bit 1 : Short Circuit Set Latched Status (SCSLS) This bit is set when Short circuit status bit is set. Bit 0 : Loss of Signal Set Latched Status (LOSSLS) This bit is set when LOS status bit is set.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RSL3 0
LRSL LIU Receive Signal Level 0806, 0A06, 0C06, 0E06
6 RSL2 0
5 RLS1 0
4 RLS0 0
3 0
2 0
1 0
0 0
Bit 7 to 4 : Receiver Signal Level 3, 2, 1, and 0 (RSL3, RSL2, RSL1, RSL0) Receive Signal Level indication. These bits are only applicable in Long Haul Mode.
Table 12-5 Receive Level Indication
RSL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RSL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RSL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RSL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Receive Level (dB) T1 >-2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20 -20 to -22.5 -22.5 to -25 -25 to -27.5 -27.5 to -30 -30 to -34 <-34 Receive Level (dB) E1 >-2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20 -20 to -22.5 -22.5 to -25 -25 to -27.5 -27.5 to -30 -30 to -34 -34 to -38 -38 to -43 <-43
Bits 3 to 0 : Unused.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Address (hex): Bit # Name Default 7 RG703 0
LRCR LIU Receive Control Register 0807, 0A07, 0C07, 0E07
6 IRTOFF 0
5 IRTS1 0
4 IRTS0 0
3 RTTR 0
2 RMME 0
1 RSMGS1 0
0 RSMGS0 0
Bit 7 : Receive G.703 Clock (RG703) When set = 1, the receiver expects a 2.048 MHz (E1 mode) or 1.544 MHz (T1 mode) synchronization clock (as specified by G.703) at RTIP/RRING. Bit 6 : Internal Receive Termination Off (IRTOFF) Disables the internal receive termination. 0 = internal receive termination enabled, IRTS1 and IRTS0 select termination value 1 = internal receive termination disabled. Bit 5 & 4 : Internal Receive Termination Select 1, 0 (IRTS1, IRTS0) These bits select the internal receive termination. These have to be set to match cable impedance. If the internal receive termination is disabled via IRTOFF, IRTS1 and IRTS2 should still be set to match the external cable characteristics for optimum operation.
Table 12-6 Internal Receive Termination Selection
IRTS0 IRTS1 INTERNAL RECEIVE TERMINATION (W) 75 100 110 120
0 0 1 1
0 1 0 1
Bit 3 : Receive Transformer Turns Ratio (RTTR) This bit is used to select receive transformer turns ratio 1:1 or 2:1 operation. 0 = 1:1 turns ratio (normal mode) 1 = 2:1 turns ratio (short haul applications only) Bit 2 : Receive Monitor Mode Enable (RMME) When set = 1, the receive monitor mode is enabled. A resistive gain will be added to the normal cable loss sensitivity. The resistive gain is determined by RSMGS1 and RSMGS0. Bits 1 & 0 : Receive Sensitivity / Monitor Gain Select 1, 0 (RSMGS1, RSMGS0) When RMME = 0, these bits are used to select the maximum receive sensitivity. When RMME = 1, these bits are used to select the receive monitor mode gain.
Table 12-7 Monitor Gain and Maximum Receive Sensitivity Selection
RMME RSMGS1 RSMGS0 MAXIMUM RECEIVE SENSITIVITY RECEIVE MONITOR GAIN SETTINGS
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
12 dB 20 dB 30 dB 36 db for T1 43 db for E1 30 dB 22.5 dB 17.5 dB 12 dB
0 0 0 0 14 20 26 32
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
13 BIT ERROR RATE TESTER (BERT)
Table 13-1 BERT Register Map
ADDRESS (hex) PORT 1 + 0h PORT 2 + 200h PORT 3 + 400h PORT 4 + 600h 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA NAME DESCRIPTION
00EB 00EC 00ED 00EE 00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF
BCR -BPCR1 BPCR2 BSPR1 BSPR2 BSPR3 BSPR4 TEICR ---BSR -BSRL -BSRIE ---RBECR1 RBECR2 RBECR3 -RBCR1 RBCR2 RBCR3 RBCR4 -----
BERT Control Register Unused BERT Pattern Configuration Register #1 BERT Pattern Configuration Register #2 BERT Seed/Pattern Register #1 BERT Seed/Pattern Register #2 BERT Seed/Pattern Register #3 BERT Seed/Pattern Register #4 Transmit Error Insertion Control Register Unused Unused Unused BERT Status Register Unused BERT Status Register Latched Unused BERT Status Register Interrupt Enable Unused Unused Unused Receive Bit Error Count Register #1 Receive Bit Error Count Register #2 Receive Bit Error Count Register #3 Unused Receive Bit Count Register #1 Receive Bit Count Register #2 Receive Bit Count Register #3 Receive Bit Count Register #4 Unused Unused Unused Unused
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
13.1 BERT Register Bit Descriptions
Register Name: Register Description: Register Address: Bit # Name Default 7 PMUM 0 6 LPMU 0
BCR BERT Control Register E0h
5 RNPL 0
4 RPIC 0
3 MPR 0
2 APRD 0
1 TNPL 0
0 TPIC 0
Bit 7/ Performance Monitoring Update Mode (PMUM) - When 0, a performance monitoring update is initiated by the LPMU register bit. When 1, a performance monitoring update is initiated by the receive performance monitoring update signal (RPMU). Note: If RPMU or LPMU is one, changing the state of this bit may cause a performance monitoring update to occur. Bit 6/ Local Performance Monitoring Update (LPMU) - This bit causes a performance monitoring update to be initiated if local performance monitoring update is enabled (PMUM = 0). A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit goes high, an update might not be performed. This bit has no affect when PMUM=1. Bit 5/ Receive New Pattern Load (RNPL) - A zero to one transition of this bit will cause the programmed test pattern (QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces the receive pattern generator out of the "Sync" state which causes a resynchronization to be initiated. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four RXCK clock cycles after this bit transitions from 0 to 1. Bit 4/ Receive Pattern Inversion Control (RPIC) - When 0, the receive incoming data stream is not altered. When 1, the receive incoming data stream is inverted. Bit 3/ Manual Pattern Resynchronization (MPR) - A zero to one transition of this bit will cause the receive pattern generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for another resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator out of the "Sync" state. Bit 2/ Automatic Pattern Resynchronization Disable (APRD) - When 0, the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the "Sync" state. Bit 1/ Transmit New Pattern Load (TNPL) - A zero to one transition of this bit will cause the programmed test pattern (QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit must be changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TXCK clock cycles after this bit transitions from 0 to 1. Bit 0/ Transmit Pattern Inversion Control (TPIC) - When 0, the transmit outgoing data stream is not altered. When 1, the transmit outgoing data stream is inverted.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 -0 6 QRSS 0
BPCR1 BERT Pattern Configuration Register #1 E2h
5 PTS 0
4 PLF4 0
3 PLF3 0
2 PLF2 0
1 PLF1 0
0 PLF0 0
Bit 6/ QRSS Enable (QRSS) - When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a generating 20 17 polynomial of x + x + 1. The output of the pattern generator will be forced to one if the next fourteen output bits are all zero. Bit 5/ Pattern Type Select (PTS) - When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive pattern. Bit 4-0/ Pattern Length Feedback (PLF[4:0]) - These five bits control the "length" feedback of the pattern generator. The "length" feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal, the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name: Register Description: Register Address: Bit # Name Default 7 -0 6 -0
BPCR2 BERT Pattern Configuration Register #2 E3h
5 -0
4 PTF4 0
3 PTF3 0
2 PTF2 0
1 PTF1 0
0 PTF0 0
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]) - These five bits control the PRBS "tap" feedback of the pattern generator. The "tap" feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
Register Name: Register Description: Register Address: Bit # Name Default 7 BSP7 0 6 BSP6 0
BSPR1 BERT Seed/Pattern Register #1 E4h
5 BSP5 0
4 BSP4 0
3 BSP3 0
2 BSP2 0
1 BSP1 0
0 BSP0 0
Bits 7 to 0: BERT Seed/Pattern (BSP[7:0])
Register Name: Register Description: Register Address: Bit # Name Default 7 BSP15 0 6 BSP14 0
BSPR2 BERT Seed/Pattern Register #2 E5h
5 BSP13 0
4 BSP12 0
3 BSP11 0
2 BSP10 0
1 BSP9 0
0 BSP8 0
Bits 7 to 0: BERT Seed/Pattern (BSP[15:8])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BSP23 0 6 BSP22 0
BSPR3 BERT Seed/Pattern Register #2 E6h
5 BSP21 0
4 BSP20 0
3 BSP19 0
2 BSP18 0
1 BSP17 0
0 BSP16 0
Bits 7 to 0: BERT Seed/Pattern (BSP[23:16])
Register Name: Register Description: Register Address: Bit # Name Default 7 BSP31 0 6 BSP30 0
BSPR4 BERT Seed/Pattern Register #2 E7h
5 BSP29 0
4 BSP28 0
3 BSP27 0
2 BSP26 0
1 BSP25 0
0 BSP24 0
Bits 7 to 0: BERT Seed/Pattern (BSP[31:24]) BERT Seed/Pattern (BSP[31:0]) - These 32 bits are the programmable seed for a transmit PRBS pattern, or the programmable pattern for a transmit or receive repetitive pattern. BSP(31) will be the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the receive side for a 32-bit repetitive pattern.
Register Name: Register Description: Register Address: Bit # Name Default 7 -0 6 -0
TEICR Transmit Error Insertion Control Register E8h
5 TEIR2 0
4 TEIR1 0
3 TEIR0 0
2 BEI 0
1 TSEI 0
0 -0
Bit 5-3/ Transmit Error Insertion Rate (TEIR[2:0]) - These three bits indicate the rate at which errors are inserted n in the output data stream. One out of every 10 bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0 th disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10 bit being inverted. A TEIR[2:0] th value of 2 result in every 100 bit being inverted. Error insertion starts when this register is written to with a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process, the new error rate will be started after the next error is inserted. Bit 2/ Bit Error Insertion Enable (BEI) - When 0, single bit error insertion is disabled. When 1, single bit error insertion is enabled. Bit 1/ Transmit Single Error Insert (TSEI) - This bit causes a bit error to be inserted in the transmit data stream if manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be inserted. Bit 0 - Unused. This bit should be set to zero for proper operation.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 -0 6 -0
BSR BERT Status Register ECh
5 -0
4 -0
3 PMS 0
2 -0
1 BEC 0
0 OOS 0
Bit 3/ Performance Monitoring Update Status (PMS) - This bit indicates the status of the receive performance monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM=1) goes low. Bit 1/ Bit Error Count (BEC) - When 0, the bit error count is zero. When 1, the bit error count is one or more. Bit 0/ Out Of Synchronization (OOS) - When 0, the receive pattern generator is synchronized to the incoming pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
Register Name: Register Description: Register Address: Bit # Name Default 7 -0 6 -0
BSRL BERT Status Register Latched EEh
5 -0
4 -0
3 PMSL 0
2 BEL 0
1 BECL 0
0 OOSL 0
Bit 3/ Performance Monitoring Update Status Latched (PMSL) - This bit is set when the PMS bit transitions from 0 to 1. Bit 2/ Bit Error Latched (BEL) - This bit is set when a bit error is detected. Bit 1/ Bit Error Count Latched (BECL) - This bit is set when the BEC bit transitions from 0 to 1. Bit 0/ Out Of Synchronization Latched (OOSL) - This bit is set when the OOS bit changes state.
Register Name: Register Description: Register Address: Bit # Name Default 7 -0 6 -0
BSRIE BERT Status Register Interrupt Enable F0h
5 -0
4 -0
3 PMSIE 0
2 BEIE 0
1 BECIE 0
0 OOSIE 0
Bit 3/ Performance Monitoring Update Status Interrupt Enable (PMSIE) - This bit enables an interrupt if the PMSL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 2/ Bit Error Interrupt Enable (BEIE) - This bit enables an interrupt if the BEL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 1/ Bit Error Count Interrupt Enable (BECIE) - This bit enables an interrupt if the BECL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 0/ Out Of Synchronization Interrupt Enable (OOSIE) - This bit enables an interrupt if the OOSL bit is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name: Register Description: Register Address: Bit # Name Default 7 BEC7 0 6 BEC6 0
RBECR1 Receive Bit Error Count Register #1 F4h
5 BEC5 0
4 BEC4 0
3 BEC3 0
2 BEC2 0
1 BEC1 0
0 BEC0 0
Bits 7 to 0: Bit Error Count (BEC[7:0])
Register Name: Register Description: Register Address: Bit # Name Default 7 BEC15 0 6 BEC14 0
RBECR2 Receive Bit Error Count Register #2 F5h
5 BEC13 0
4 BEC12 0
3 BEC11 0
2 BEC10 0
1 BEC9 0
0 BEC8 0
Bits 7 to 0: Bit Error Count (BEC[15:8])
Register Name: Register Description: Register Address: Bit # Name Default 7 BEC23 0 6 BEC22 0
RBECR3 Receive Bit Error Count Register #3 F6h
5 BEC21 0
4 BEC20 0
3 BEC19 0
2 BEC18 0
1 BEC17 0
0 BEC16 0
Bits 7 to 0: Bit Error Count (BEC[23:16]) Bit Error Count (BEC[23:0]) - These twenty-four bits indicate the number of bit errors detected in the incoming data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit error counter will not incremented when an OOS condition exists.
Register Name: Register Description: Register Address: Bit # Name Default 7 BC7 0 6 BC6 0
RBCR1 Receive Bit Count Register #1 F8h
5 BC5 0
4 BC4 0
3 BC3 0
2 BC2 0
1 BC1 0
0 BC0 0
Bits 7 to 0: Bit Count (BC[7:0])
Register Name: Register Description: Register Address: Bit # Name Default 7 BC15 0 6 BC14 0
RBCR2 Receive Bit Count Register #2 F9h
5 BC13 0
4 BC12 0
3 BC11 0
2 BC10 0
1 BC9 0
0 BC8 0
Bits 7 to 0: Bit Count (BC[15:8])
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BC23 0 6 BC22 0
RBCR3 Receive Bit Count Register #3 FAh
5 BC21 0
4 BC20 0
3 BC19 0
2 BC18 0
1 BC17 0
0 BC16 0
Bits 7 to 0: Bit Count (BC[23:16])
Register Name: Register Description: Register Address: Bit # Name Default 15 BC31 0 14 BC30 0
RBCR4 Receive Bit Count Register #4 FBh
13 BC29 0
12 BC28 0
11 BC27 0
10 BC26 0
9 BC25 0
8 BC24 0
Bits 7 to 0: Bit Count (BC[31:24]) Bit Count (BC[31:0]) - These thirty-two bits indicate the number of bits in the incoming data stream. This count stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter will not incremented when an OOS condition exists.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
14 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26556 JTAG port supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26556 contains the following, as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register
The Test Access Port has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details.
Figure 14-1 JTAG Functional Block Diagram
BOUNDRY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER TEST ACCESS PORT CONTROLLER VDD
10kW
MUX
SELECT OUTPUT ENABLE
VDD
10kW
VDD
10kW
JTDI
JTMS
JTCLK
JTRST
JTDO
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
14.1 TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 14-2.
Figure 14-2 Tap Controller State Diagram
1 Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1
0
Test-Logic-Reset Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test registers will remain idle. Select-DR-Scan All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. Capture-DR Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.
Shift-DR The test data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. Exit1-DR While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-DR state. Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state. Exit2-DR A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-DR state. Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Exit1IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state. Shift-IR In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel register and all test registers remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register. Exit1-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process. Pause-IR Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. Exit2-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller enters the Select-DR-Scan state.
14.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26556 and its respective operational binary codes are shown in Table 14-1.
Table 14-1 Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001
SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift-DR state. BYPASS When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation. EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register. CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. HIGHZ All digital outputs of the device will be placed in a high-impedance state. The BYPASS register will be connected between JTDI and JTDO. IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver will always have a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
Table 14-2 ID Code Structure
MSB Version (contact factory) 4 bits
Device ID (0038h) 0000000000111000
JEDEC 00010100001
LSB (Must be '1') 1 1
14.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers--the bypass register and the boundary scan register. An optional test register, the identification register, has been included with the DS26556 design. The identification register is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Boundary Scan Register This register contains a shift register path and a latched parallel output for all control cells and digital I/O cells. It is n bits in length. Bypass Register The bypass register is a single one-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions, which provide a short path between JTDI and JTDO. Identification Register The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
15 PIN ASSIGNMENT
Figure 15-1 DS26556 Pin Assignments--256-Lead BGA
1 A B C D E F G H J K L M N P R T
TTIP1 TVDD1 RTIP1 RVDD1 RVDD2 RTIP2 TVDD2 TTIP2 TTIP3 TVDD3 RTIP3 RVDD3 RVDD4 RTIP4 TVDD4 TTIP4
2
STTIP1 TVSS1 RRING1 RVSS1 RVSS2 RRING2 TVSS2 STTIP2 STTIP3 TVSS3 RRING3 RVSS3 RVSS4 RRING4 TVSS4 STTIP4
3
TRING1 STRING1 TSYNC1 RSYNC1 TSYNC2 TSERI2 STRING2 TRING2 TRING3 STRING3 RLOS4 HIZ TCLK3 TCHMRK3 STRING4 TRING4
4
TSERI1 RCHMRK1 RCLKO1 GTEST1 GTEST2 RLOS1 RLOF_LOTC2 RLOS2 RM_RFSYNC1 RM_RFSYNC2 RM_RFSYNC4 RLOS3 RLOF_LOTC4 TCLK4 TSERI4 RCHMRK4
5
RSYNC2 RSER2 TCLK1 TSERO1 RSER1 RLOF_LOTC1 VDD VDD VSS VSS RM_RFSYNC3 TXENABLE TCHMRK4 TSYNC4 RSYNC4 RSER4
6
TCLK2 TCHMRK2 RCHMRK2 TSERO2 RCLKO2 TCHMRK1 VDD VDD VSS VSS RLOF_LOTC3 TSERO4 RCHMRK3 TSERO3 TSYNC3 TSERI3
7
ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 VDD VDDCC VDD VSS RCLKO4 RCLKO3 RSER3 RTEST3 RTEST1 RTEST2
8
ADDR4 ADDR3 ADDR5 ADDR2 ADDR6 ADDR1 VDD VSSCC VSS VSS RSYNC3 TTEST3 TTEST2 SCAN_EN RESET SCAN_MODE
9
REFCLK ADDR0 MCLK BPCLK DATA7 DATA6 VDD VDD VSS VSS TTEST1 HSYSCLK HSSYNC HTSIG HRDATA HTDATA
10
DATA4 DATA5 DATA3 DATA2 DATA1 DATA0 VDD VDD VSS VSS HRSIG JTDO JTDI JTRST JTCLK JTMS
11
WR CS RD BTS TADR1 TDXA4 VDD VDD VSS VSS RLCD4 ROCD1 RLCD3 RLCD2 ROCD4 RLCD1
12
TADR0 INT TPAR TADR3 TDAT8 RSOX VDD RDAT14 RADR4 VSS TDAT6 TDAT15 TERR TSOX TSX TEOP
13
TADR4 TADR2 TEN TDAT9 RERR RMOD RDAT11 RDAT15 RDAT6 RADR3 TDAT4 TDAT5 TDAT7 TDAT10 TDAT12 TDAT11
14
RDXA3 NC TDXA2 REN VSS TMOD NC RSCLK RDAT5 NC TDAT14 TDAT13 ROCD3 ROCD2 NC TDAT1
15
NC RDXA2 TDXA1 RDXA1 RVAL RPAR REOP NC NC RDAT10 RDAT9 RDAT13 RADR0 RADR1 TDAT0 NC
16
RDXA4 TDXA3 TSPA TSCLK NC RDAT0 RDAT2 RDAT1 RDAT4 RDAT3 RDAT8 RDAT7 RDAT12 RADR2 TDAT3 TDAT2
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
16 PACKAGE MECHANICAL INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
NOTES: 1. 2. 3. 4. 5. DIMENSION IS MM. THE BASIC SOLDER BALL GRID PITCH IS 1.00 MM. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. A1 BALL PAD CORNER ID
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
17 PACKAGE THERMAL INFORMATION
Table 17-1 Thermal Characteristics
PARAMETER MIN TYP MAX
Ambient Temperature (Note 1) Junction Temperature Theta-JA (qJA) in Still Air for 10mm CSBGA
Note 1: Note 2:
-40C -
17.5
+85C +125C -
The package is mounted on a four-layer JEDEC standard test board. Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board.
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18 ABSOLUTE MAXIMUM RATINGS
Table 18-1 Absolute Maximum Ratings
Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS26556 Operating Temperature Range for DS26556N Storage Temperature Range Soldering Temperature -1.0V to +6.0V 0C to +70C -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020 Standard
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
Table 18-2 Recommended DC Operating Conditions
(TA = 0C to +70C for DS26556; TA = -40C to +85C for DS26556N.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Logic 1 Logic 0 Supply
VIH VIL VDD
(Note 1)
2.0 -0.3 3.135
3.3
5.5 +0.8 3.465
V V V
Table 18-3 Capacitance
(TA = +25C)
PARAMETER SYMBOL MIN TYP MAX UNITS
Input Capacitance Output Capacitance
CIN COUT
5 7
pF pF
Table 18-4 DC Operating Characteristics
(VDD = 3.3V 5%, TA = 0C to +70C for DS26556; VDD = 3.3V 5%, TA = -40C to +85C for DS26556N.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V)
Note 1: Note 2: Note 3:
IDD IIL ILO IOH IOL
(Note 1) (Note 2) (Note 3)
300 -1.0 -1.0 +4.0 +1.0 1.0
mA mA mA mA mA
Measured with all four ports operating in E1 LBO 0 mode with a 50% ones density and the system interface operating at 52MHz. 0.0V < VIN < VDD. Applied to INT when tri-stated.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19 AC TIMING
Unless otherwise noted, all timing numbers assume 25pF test load on output signals, 40pF test load on bus signals. There are several common AC characteristic definitions. These generic definitions are shown below in Figure 19-1, Figure 19-2, Figure 19-3, and Figure 19-4. Definitions that are specific to a given interface are shown in that interface's subsection.
Figure 19-1 Clock Period and Duty Cycle Definitions
t1
Clock t2 t2
Figure 19-2 Rise Time, Fall Time, and Jitter Definitions
t1 t4/2
Clock t3 t3 t4
Figure 19-3 Hold, Setup, and Delay Definitions (Rising Clock Edge)
Clock t5 Din t7 Dout t6
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 19-4 Hold, Setup, and Delay Definitions (Falling Clock Edge)
Clock t5 Din t7 Dout t6
Figure 19-5 To/From High-Z Delay Definitions (Rising Clock Edge)
Clock t8 Dout t9
Figure 19-6 To/From High-Z Delay Definitions (Falling Clock Edge)
Clock t8 Dout t9
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.1 Transmit TDM Port AC Characteristics
All AC timing characteristics are specified with a 25 pF capacitive load on all output pins, VIH = 2.4V and VIL = 0.8V. The voltage threshold for all timing measurements is VDD/2. The generic timing definitions shown in Figure 19-1, Figure 19-2, Figure 19-3, and Figure 19-6 apply to this interface.
Table 19-1 Transmit TDM Port Timing
(VDD = 3.3V 5%, Tj = -40C to +85C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TCLK Period TCLK Clock Duty Cycle (t2/t1) TSERI, TSYNC to TCLK Setup Time TCLK to TSERI, TSYNC Hold Time TCLK to TSERO, TSYNC, TCHMRK Delay
t1 t1 t2/t1 t5 t6 t7
T1 mode E1 mode 125 20 20
648 488
ns ns ns ns ns 50 ns
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.2 Receive TDM Port AC Characteristics
All AC timing characteristics are specified with a 25 pF capacitive load on all output pins, VIH = 2.4V and VIL = 0.8V. The voltage threshold for all timing measurements is VDD/2. The generic timing definitions shown in Figure 19-1, Figure 19-2, Figure 19-3, and Figure 19-6 apply to this interface.
Table 19-2 Receive TDM Port Timing
(VDD = 3.3V 5%, Tj = -40C to +85C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RCLKO Period RCLKO Clock Duty Cycle (t2/t1) RCLKO to RSER, RSYNC, RM_RFSYNC, RCHMRK Delay
t1 t1 t2/t1 t7
T1 mode E1 mode 125
648 488
ns ns ns 50 ns
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.3 High Speed Port AC Characteristics
All AC timing characteristics are specified with a 25 pF capacitive load on all output pins, VIH = 2.4V and VIL = 0.8V. The voltage threshold for all timing measurements is VDD/2. The generic timing definitions shown in Figure 19-1, Figure 19-2, Figure 19-3, and Figure 19-6 apply to this interface.
Table 19-3 Receive TDM Port Timing
(VDD = 3.3V 5%, Tj = -40C to +85C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HSYSCLK Period HSYSCLK Clock Duty Cycle (t2/t1) HTDATA, HTSIG, HSSYNC to HSYSCLK Setup Time HSYSCLK to HTDATA, HTSIG, HSSYNC Hold Time HSYSCLK to HRDATA, HRSIG, HSSYNC Delay
t1 t1 t2/t1 t5 t6 t7
T1 mode E1 mode
60 60 30 20 20 50
ns ns ns ns ns ns
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.4 System Interface AC Characteristics
The generic timing definitions shown in Figure 19-1, Figure 19-2, Figure 19-3, and Figure 19-6 apply to this interface.
Table 19-4 System Interface Level 2 Timing
(VDD = 3.3V 5%, Tj = -40C to +125C.)
SIGNAL NAME(S) SYMBOL DESCRIPTION MIN TYP MAX UNITS
RSCLK and TSCLK RSCLK and TSCLK RSCLK and TSCLK RADR and REN RADR and REN RDATA, RPRTY, RPXA, RSOX, REOP, RVAL, RMOD, and RERR RDATA, RPRTY, RPXA, RSOX, REOP, RVAL, RMOD, and RERR RDATA, RPRTY, RPXA, RSOX, REOP, RVAL, RMOD, and RERR TDATA, TPRTY, TADR, TEN, TSOX, TEOP, TMOD, and TERR TDATA, TPRTY, TADR, TEN, TSOX, TEOP, TMOD, and TERR TPXA and TSPA TPXA and TSPA TPXA and TSPA
Note 1: Note 2: Note 3:
f1 t2/t1 t3 t5 t6 t7 t8 t9 t5 t6 t7 t8 t9
Clock frequency (1/t1) (Note 1) Clock duty cycle (Note 1) Rise/fall times (Notes 1, 2) Hold time from RSCLK (Note 1) Setup time to RSCLK (Note 1) Delay from RSCLK (Notes 1, 3) From high-Z delay from RSCLK (Notes 1, 3) To high-Z delay from RSCLK (Notes 1, 3) Hold time from TSCLK (Note 1) Setup time to TSCLK (Note 1) Delay from TSCLK (Notes 1, 3) From high-Z delay from TSCLK (Notes 1, 3) To high-Z delay from TSCLK (Notes 1, 3)
0 40 50
52 60 2
MHz % ns ns ns
0 3.5 2 2 2 0 3.5 2 2 2 12 12 15 12 12 15
ns ns ns ns ns ns ns ns
The input/output timing reference level for all signals is VDD/2. Rise and fall times are measured at output side with the output unloaded. Rise time is measured from 20% to 80% VOH. Fall time is measured from 80% to 20% VOH. These times are met with a 30pF, 300W load on the associated output pin.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Table 19-5 System Interface Level 3 Timing
(VDD = 3.3V 5%, Tj = -40C to +125C.)
SIGNAL NAME(S) SYMBOL DESCRIPTION MIN TYP MAX UNITS NOTES
RSCLK and TSCLK RSCLK and TSCLK RSCLK and TSCLK RADR and REN RADR and REN RDATA, RPRTY, RPXA, RSOX, REOP, RVAL, RMOD, and RERR TDATA, TPRTY, TADR, TEN, TSOX, TEOP, TMOD, and TERR TDATA, TPRTY, TADR, TEN, TSOX, TEOP, TMOD, and TERR TPXA and TSPA
Note 1: Note 2: Note 3:
f1 t2/t1 t3 t5 t6 t7
Clock Frequency (1/t1) Clock Duty Cycle Rise/Fall Times Hold Time from RSCLK Setup Time to RSCLK Delay from RSCLK
0 40 0 3.5 2 50
52 60 2
MHz % ns ns ns
1 1 1,2 1 1 1,3
12
ns
t5
Hold Time from TSCLK
0
ns
1
t6 t7
Setup Time to TSCLK Delay from TSCLK
3.5 2 12
ns ns
1 1,3
The input/output timing reference level for all signals is VDD/2. Rise and fall times are measured at output side with the output unloaded. Rise time is measured from 20% to 80% VOH. Fall time is measured from 80% to 20% VOH. These times are met with a 30pF, 300W load on the associated output pin.
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.5 Microprocessor Bus AC Characteristics Table 19-6 AC Characteristics--Microprocessor Bus Timing
(VDD = 3.3V 5%, TA = 0C to +70C for DS26556; VDD = 3.3V 5%, TA = -40C to +85C for DS26556N.) (Figure 19-7, Figure 19-8, Figure 19-9, and Figure 19-10)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for ADDR[12:0] Valid to CS Active Setup Time for CS Active to Either RD or WR Active Delay Time from Either RD or DS Active to D[7:0] Valid Hold Time from Either RD or WR Inactive to CS Inactive Hold Time from CS or RD or DS Inactive to DATA[7:0] Tri-State Wait Time from WR Active to Latch Data Data Set Up Time to WR Inactive Data Hold Time from WR Inactive Address Hold from WR Inactive Write Access to Subsequent Write/Read Access Delay Time
Note 1: Guaranteed by design.
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
(Note 1) (Note 1)
0 0 115 0 2.5 35 10 2 3 80 20
ns ns ns ns ns ns ns ns ns ns
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 19-7 Intel Bus Read Timing (BTS = 0)
ADDR[12:0] DATA[7:0]
Address Valid Data Valid t5
WR
t1
CS
t2 RD*
t3
t4 t10
Figure 19-8 Intel Bus Write Timing (BTS = 0)
ADDR[12:0] DATA[7:0]
Address Valid
t7
RD
t8
t1
CS
t2
WR
t6
t4 t10
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Figure 19-9 Motorola Bus Read Timing (BTS = 1)
ADDR[12:0] DATA[7:0] R/W t1
CS
Address Valid Data Valid t5
t2
DS
t3
t4 t10
Figure 19-10 Motorola Bus Write Timing (BTS = 1)
ADDR[12:0] DATA[7:0] R/W t1
CS
Address Valid
t7 t8
t2
DS
t6
t4 t10
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.6 JTAG Interface Timing Table 19-7 JTAG Interface Timing
(VDD = 3.3V 5%, TA = -40C to +85C.) (Figure 19-11)
PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO High-Z Delay JTRST Width Low Time
Note 1: Clock can be stopped high or low.
SYMBOL t1 t2/t3 t4 t5 t6 t7 t8
CONDITIONS (Note 1)
MIN 50 3 2 2 2 100
TYP 1000 500
MAX
UNITS ns ns ns ns ns ns ns
50 50
Figure 19-11 JTAG Interface Timing Diagram
t1 t2 t3
JTCLK t4 JTDI, JTMS, JTRST t6 t7 t5
JTD0
t8 JTRST
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DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
20 REVISION CHANGE HISTORY
DATE DESCRIPTION
012105
New Product Release
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Ma x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0 (c) 2005 Maxim Integrated Products * Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

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